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2017 HR1384 / KRL Test Hints


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Regulation (Vnl-Vfl)/Vfl is Load regulation
Rectification Efficiency full wave 82.2%
USB Un‫۔‬equalling conductors
Find Io
Class A Full Cycle Current
Class B has Cross over distortion
Class AB stable ...
Alpha open loop gain, beta closed loop.. negative feedback gain by factor ..
Pentavalent
Germanium diode potential barriers
Avalanche or Zener
Collector feedback
CE current gain
OP-AMP output non-inverting
Subtractor
Darlington characteristics
Soft processor FPGA
Multistage effects on gain and frequency
OR gate function/circuit output at given combination
Not gate definition
A+0, A+1, A.Abar
Collpit/weign/hartley
Oscillator + crystal + stability of frequency
Avg value of 3 phase output
Or gate using diodes(also in 2018)
Absolute function (also in 2018)
Resistance Equivalent (also in 2018)
Opamp Integrator output if step function is input (similar in 2018)
Even symmetry
Output of Schmidt ( square at sine input) trigger+asymmetric square wave
Inductive current output is DC if ac source at input something like this
Capacitor would explode if the polarity is reversed...
Diode Limiter output 0 or not ... circuit

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