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Csd87350Q5D Synchronous Buck Nexfet™ Power Block: 1 Features 3 Description
Csd87350Q5D Synchronous Buck Nexfet™ Power Block: 1 Features 3 Description
CSD87350Q5D
SLPS288E – MARCH 2011 – REVISED FEBRUARY 2017
2 Applications TGR 4 5 BG
• IMVP, VRM, and VRD Applications (1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Circuit Typical Power Block Efficiency and Power Loss
VIN 96 11
BOOT 94 10
VDD VDD
VIN
TG 92 9
DRVH Control
GND FET 90 8
VGS = 5 V
88 7
ENABLE ENABLE
LL VOUT VIN = 12 V
Sync 86 VOUT = 1.3 V 6
PWM PWM BG FET LOUT = 0.3 PH
DRVL 84 fSW = 500 kHz 5
PGND
82 TA = 25qC 4
Driver IC CSD87350Q5D
80 3
78 2
76 1
74 0
0 5 10 15 20 25 30 35 40
Output Current (A) D001
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD87350Q5D
SLPS288E – MARCH 2011 – REVISED FEBRUARY 2017 www.ti.com
Table of Contents
1 Features .................................................................. 1 7 Layout ................................................................... 15
2 Applications ........................................................... 1 7.1 Layout Guidelines ................................................... 15
3 Description ............................................................. 1 7.2 Layout Example ...................................................... 16
4 Revision History..................................................... 2 8 Device and Documentation Support.................. 17
5 Specifications......................................................... 3 8.1 Documentation Support .......................................... 17
5.1 Absolute Maximum Ratings ...................................... 3 8.2 Receiving Notification of Documentation Updates.. 17
5.2 Recommended Operating Conditions....................... 3 8.3 Community Resources............................................ 17
5.3 Thermal Information .................................................. 3 8.4 Trademarks ............................................................. 17
5.4 Power Block Performance ........................................ 3 8.5 Electrostatic Discharge Caution .............................. 17
5.5 Electrical Characteristics........................................... 4 8.6 Glossary .................................................................. 17
5.6 Typical Power Block Device Characteristics............. 5 9 Mechanical, Packaging, and Orderable
5.7 Typical Power Block MOSFET Characteristics......... 7 Information ........................................................... 18
9.1 Q5D Package Dimensions...................................... 18
6 Application and Implementation ........................ 10
9.2 Land Pattern Recommendation .............................. 19
6.1 Application Information............................................ 10
9.3 Stencil Recommendation ........................................ 19
6.2 Typical Application .................................................. 13
9.4 Q5D Tape and Reel Information ............................. 20
4 Revision History
Changes from Revision D (September 2014) to Revision E Page
• Added note for IDM in the Absolute Maximum Ratings table .................................................................................................. 3
• Added Receiving Notification of Documentation Updates section and Community Resources section in the
Documentation Support section ........................................................................................................................................... 17
• Added Handling Rating table, Application and Implementation section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1
• Changed "DIM a" Millimeter Max value From: 1.55 To: 1.5 and Inches Max value From: 0.061 To: 0.059........................ 18
• Changed Power Dissipation, PD in the Absolute Maximum Ratings table From; 13 W to 12 W............................................ 3
5 Specifications
5.1 Absolute Maximum Ratings
TA = 25°C (unless otherwise noted) (1)
MIN MAX UNIT
VIN to PGND –0.8 30 V
Voltage TG to TGR –8 10 V
BG to PGND –8 10 V
IDM Pulsed current rating (2) 120 A
PD Power dissipation 12 W
Sync FET, ID = 105 A, L = 0.1 mH 551
EAS Avalanche energy mJ
Control FET, ID = 60 A, L = 0.1 mH 180
TJ Operating junction temperature –55 150 °C
Tstg Storage temperature –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Pulse duration ≤ 50 µs. Duty cycle ≤ 0.01%.
(3.81-cm × 3.81-cm), 0.06-in (1.52-mm) thick FR4 board. RθJC is specified by design while RθJA is determined by the user’s board
design.
(1) Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins and
using a high-current 5-V driver IC.
(1) Equivalent based on application testing. See Equivalent System Performance section for details.
HD LD HD LD
5x6 QFN TTA MIN Rev1
LG HS LG HS
HG LS HG LS
M0189-01 M0190-01
10 1.05
9 1
8
6 0.9
5 0.85
4 0.8
3
0.75
2
1 0.7
0 0.65
0 5 10 15 20 25 30 35 40 -50 -30 -10 10 30 50 70 90 110 130 150
Output Current (A) D002
TC - Junction Temperature (qC) D003
Figure 1. Power Loss vs Output Current Figure 2. Normalized Power Loss vs Temperature
45 45
40 40
35 35
Output Current (A)
Output Current (A)
30 30
25 25
20 20
15 15
Figure 3. Safe Operating Area (SOA) – PCB Vertical Mount Figure 4. Safe Operating Area (SOA) – PCB Horizontal
Mount
45 1.5 14.7
40
1.4 11.8
30 1.3 8.8
25
1.2 5.9
20
15 1.1 2.9
10
1 0.0
5
0 0.9 -2.9
0 20 40 60 80 100 120 140 200 400 600 800 1000 1200 1400 1600
Board Temperature (qC) D006
Switching Frequency (kHz) D007
Figure 5. Typical Safe Operating Area (SOA) Figure 6. Normalized Power Loss vs Switching Frequency
1.25 -7.3
1.15 4.4
1.2 -5.9
1.1 2.9 1.15 -4.4
1.1 -2.9
1.05 1.5
1.05 -1.5
1 0.0
1 0.0
0.95 1.5
0.95 -1.5 0.9 2.9
0 2 4 6 8 10 12 14 16 18 20 22 24 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5
Input Voltage (V) D008
Output Voltage (V) D009
VIN = 12 V VOUT = 1.3 V LOUT = 0.3 µH VIN = 12 V VGS = 5 V ƒSW = 500 kHz
ƒSW = 500 kHz IOUT = 40 A LOUT = 0.3 µH IOUT = 40 A
Figure 7. Normalized Power Loss vs Input Voltage Figure 8. Normalized Power Loss vs Output Voltage
1.125 3.7
1.1 2.9
1.075 2.2
1.05 1.5
1.025 0.7
1 0.0
0.975 -0.7
0.95 -1.5
0.925 -2.2
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1
Output Inductance (PH) D010
80 80
70 70
IDS - Drain-to-Source Current (A)
50 50
40 40
30 30
20 20
VGS = 8.0 V VGS = 8.0 V
10 VGS = 4.5 V 10 VGS = 4.5 V
VGS = 4.0 V VGS = 4.0 V
0 0
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2
VDS - Drain-to-Source Voltage (V) D011
VDS - Drain-to-Source Voltage (V) D012
Figure 10. Control MOSFET Saturation Figure 11. Sync MOSFET Saturation
100 100
IDS - Drain-to-Source Current (A)
1 1
0.1 0.1
VDS = 5 V VDS = 5 V
Figure 12. Control MOSFET Transfer Figure 13. Sync MOSFET Transfer
8 8
7 7
VGS - Gate-to-Source Voltage (V)
6 6
5 5
4 4
3 3
2 2
1 1
0 0
0 2 4 6 8 10 12 14 16 0 5 10 15 20 25 30 35
Qg - Gate Charge (nC) D015
Qg - Gate Charge (nC) D016
ID = 20 A VDD = 15 V ID = 20 A VDD = 15 V
Figure 14. Control MOSFET Gate Charge Figure 15. Sync MOSFET Gate Charge
1 1
C - Capacitance (nF)
C - Capacitance (nF)
0.1 0.1
0.01 0.01
Ciss = Cgd + Cgs Ciss = Cgd + Cgs
Coss = Cds + Cgd Coss = Cds + Cgd
Crss = Cgd Crss = Cgd
0.001 0.001
0 3 6 9 12 15 18 21 24 27 30 0 3 6 9 12 15 18 21 24 27 30
VDS - Drain-to-Source Voltage (V) D017
VDS - Drain-to-Source Voltage (V) D018
Figure 16. Control MOSFET Capacitance Figure 17. Sync MOSFET Capacitance
1.8 1.4
1.6 1.2
VGS(th) - Threshold Voltage (V)
1.2 0.8
1 0.6
0.8 0.4
0.6 0.2
-75 -50 -25 0 25 50 75 100 125 150 175 -75 -50 -25 0 25 50 75 100 125 150 175
TC - Case Temperature (°C) D019
TC - Case Temperature (°C) D020
ID = 250 µA ID = 250 µA
Figure 18. Control MOSFET VGS(th) Figure 19. Sync MOSFET VGS(th)
16 8
TC = 25°C TC = 25°C
RDS(on) - On-State Resistance (m:)
14 TC = 125°C 7 TC = 125°C
12 6
10 5
8 4
6 3
4 2
2 1
0 0
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10
VGS - Gate-to-Source Voltage (V) D021
VGS - Gate-to-Source Voltage (V) D022
Figure 20. Control MOSFET RDS(on) vs VGS Figure 21. Sync MOSFET RDS(on) vs VGS
1.4 1.4
Normalized On-State Resistance
1.2 1.2
1.1 1.1
1 1
0.9 0.9
0.8 0.8
0.7 0.7
-75 -50 -25 0 25 50 75 100 125 150 175 -75 -50 -25 0 25 50 75 100 125 150 175
TC - Case Temperature (°C) D023
TC - Case Temperature (°C) D001
D024
ID = 20 A VGS = 8 V ID = 20 A VGS = 8 V
Figure 22. Control MOSFET Normalized RDS(on) Figure 23. Sync MOSFET Normalized RDS(on)
100 100
ISD - Source-to-Drain Current (A)
1 1
0.1 0.1
0.01 0.01
0.001 0.001
TC = 25°C TC = 25°C
TC = 125°C TC = 125°C
0.0001 0.0001
0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1
VSD - Source-to-Drain Voltage (V) D025
VSD - Source-to-Drain Voltage (V) D026
Figure 24. Control MOSFET Body Diode Figure 25. Sync MOSFET Body Diode
100 1000
TC = 25°C TC = 25°C
TC = 125°C TC = 125°C
IAV - Peak Avalanche Current (A)
IAV - Peak Avalanche Current (A)
100
10
10
1 1
0.01 0.1 1 10 0.01 0.1 1 10
tAV - Time in Avalanche (ms) D027
tAV - Time in Avalanche (ms) D028
Figure 26. Control MOSFET Unclamped Inductive Switching Figure 27. Sync MOSFET Unclamped Inductive Switching
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
+ Ci
Input Driver Control
Supply - PWM FET
Switch Lo
Node Co
Driver Sync IL
FET Load
The CSD87350Q5D is part of TI’s power block product family which is a highly optimized product for use in a
synchronous buck topology requiring high current, high efficiency, and high frequency. It incorporates TI’s latest
generation silicon which has been optimized for switching performance, as well as minimizing losses associated
with QGD, QGS, and QRR. Furthermore, TI’s patented packaging technology has minimized losses by nearly
eliminating parasitic elements between the control FET and sync FET connections (see Figure 29). A key
challenge solved by TI’s patented packaging technology is the system level impact of Common Source
Inductance (CSI). CSI greatly impedes the switching characteristics of any MOSFET which in turn increases
switching losses and reduces system efficiency. As a result, the effects of CSI need to be considered during the
MOSFET selection process. In addition, standard MOSFET switching loss equations used to predict system
efficiency need to be modified in order to account for the effects of CSI. Further details behind the effects of CSI
and modification of switching loss equations are outlined in Power Loss Calculation With Common Source
Inductance Consideration for Synchronous Buck Converters (SLPA009).
Input
Supply
RPCB CESR
LDRAIN
CINPUT
Driver Control
PWM FET
CESL
LSOURCE
Switch Lo
Node Co
IL
LDRAIN Load
Sync CTOTAL
Driver
FET
LSOURCE
The combination of TI’s latest generation silicon and optimized packaging technology has created a
benchmarking solution that outperforms industry standard MOSFET chipsets of similar RDS(ON) and MOSFET
chipsets with lower RDS(ON). Figure 30 and Figure 31 compare the efficiency and power loss performance of the
CSD87350Q5D versus industry standard MOSFET chipsets commonly used in this type of application. This
comparison purely focuses on the efficiency and generated loss of the power semiconductors only. The
performance of CSD87350Q5D clearly highlights the importance of considering the Effective AC On-Impedance
(ZDS(ON)) during the MOSFET selection process of any new design. Simply normalizing to traditional MOSFET
RDS(ON) specifications is not an indicator of the actual in-circuit performance when using TI’s power block
technology.
96 11
Power Block HS/LS RDS(on) = 5 m: / 2.1 m:
10
93 Discrete HS/LS RDS(on) = 5 m: / 2.1 m:
9 Discrete HS/LS RDS(on) = 5 m: / 1.2 m:
90 8
VGS = 5 V
Power Loss (W)
Efficiency (%)
87 VIN = 12 V 7 VGS = 5 V
VOUT = 1.3 V 6 VIN = 12 V
84 LOUT = 0.3 PH VOUT = 1.3 V
fSW = 500 kHz 5 LOUT = 0.3 PH
81 TA = 25qC 4 fSW = 500 kHz
TA = 25qC
78 3
Power Block HS/LS RDS(on) = 5 m: / 2.1 m: 2
75 Discrete HS/LS RDS(on) = 5 m: / 2.1 m:
1
Discrete HS/LS RDS(on) = 5 m: / 1.2 m:
72 0
0 5 10 15 20 25 30 35 40 45 0 5 10 15 20 25 30 35 40 45
Output Current (A) D029
Output Current (A) D030
Figure 30. Efficiency Figure 31. Power Loss
A VIN
BOOT
VDD A VDD V
VIN Input Voltage (VIN)
Gate Drive V TG
Voltage (VDD) DRVH
ENABLE
Output Current (IOUT)
TGR VSW
LL A VOUT
PWM
PWM BG
DRVL PGND
GND
Averaged Switch
CSD87350Q5D Averaging
Driver IC V Node Voltage
Circuit
(VSW_AVG)
Figure 32.
7 Layout
(1) Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of
Missouri – Rolla
Copyright © 2011–2017, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: CSD87350Q5D
CSD87350Q5D
SLPS288E – MARCH 2011 – REVISED FEBRUARY 2017 www.ti.com
Input Capacitors
Input Capacitors
TGR TG VIN
RC Snubber
Power Block
Location on Top
Layer
8.4 Trademarks
NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
8.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
8.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
5
5
4
b
3
6
6
3
9
E D1 D2
7
2
7
2
d e
1
8
8
d3
f
Top View Side View Bottom View
Pinout
Position Designation
Pin 1 VIN
Exposed Tie Bar May Vary
q Pin 2 VIN
Pin 3 TG
Pin 4 TGR
a
Pin 5 BG
Pin 6 VSW
c Pin 7 VSW
E1 VSW
Pin 8
Front View Pin 9 PGND
M0187-01
MILLIMETERS INCHES
DIM
MIN MAX MIN MAX
a 1.40 1.5 0.055 0.059
b 0.360 0.460 0.014 0.018
c 0.150 0.250 0.006 0.010
c1 0.150 0.250 0.006 0.010
d 1.630 1.730 0.064 0.068
d1 0.280 0.380 0.011 0.015
d2 0.200 0.300 0.008 0.012
d3 0.291 0.391 0.012 0.015
D1 4.900 5.100 0.193 0.201
D2 4.269 4.369 0.168 0.172
E 4.900 5.100 0.193 0.201
E1 5.900 6.100 0.232 0.240
E2 3.106 3.206 0.122 0.126
e 1.27 TYP 0.050
f 0.396 0.496 0.016 0.020
L 0.510 0.710 0.020 0.028
θ 0.00 — — —
K 0.812 0.032
4
5
4.460
0.620
(0.176) 0.620 (0.024)
(0.024)
4.460
(0.176)
1.270 1.920
(0.050) (0.076)
1
8
6.240 (0.246)
M0188-01
0.300 (0.012)
1.710
(0.067) 1.680
(0.066)
1
8
PCB Pattern
M0208-01
For recommended circuit layout for PCB designs, see Reducing Ringing Through PCB Layout Techniques
(SLPA005).
5.50 ±0.05
12.00 ±0.30
B0
A0 = 5.30 ±0.10
B0 = 6.50 ±0.10
K0 = 1.90 ±0.10
M0191-01
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PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 2
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