CompactFlash Core with Avalon Interface

Core Overview
The CompactFlash Core with Avalon Interface (“the CompactFlash core”)
implements a method of communicating between a CompactFlash Storage Card in
True IDE Mode and an embedded system on an Altera FPGA. The core
implements the CompactFlash True IDE Mode timing and provides a direct
Avalon interface to the registers on the CompactFlash device.

The core provides a simple register-mapped Avalon slave interface that allows
Avalon master peripherals (such as a Nios II processor) to communicate with the
core simply by reading and writing control and data registers.

The CompactFlash core is SOPC Builder-ready and integrates easily into any
SOPC Builder- generated system.

Quick Reference

Functional Description
Figure X shows a block diagram of the CompactFlash core.

Altera FPGA
CompactFlash core

CompactFlash Slot
address

data ide
port Avalon-to-
CompactFlash
IRQ
Avalon
signals
connected
to on-chip
logic address cfctl
data ctl
port
IRQ
idectl

Avalon Slave Interface and Registers

The CompactFlash core provides two Avalon slave interfaces, one for accessing
the registers inside the CompactFlash device and the second for the core’s internal
 register file. A master peripheral, such as a Nios II processor, accesses the
registers to control the core and transfer data to and from the CompactFlash
device.

The CompactFlash core provides two active-high interrupt request (IRQ) outputs.
One interrupt signals the insertion or removal of a CompactFlash device; the
second passes the interrupt signal from the device on to the Avalon master.

CompactFlash Interface
The CompactFlash core maps the Avalon bus signals to the CompactFlash device
with the proper timing, allowing an Avalon master direct access to registers in the
device. More information can be found in the CF+ and CompactFlash
Specification.

Device & Tools Support

The UART core can target all Altera FPGAs, including Stratix and Cyclone
device families.

Instantiating the Core in SOPC Builder

Instantiating the CompactFlash core in hardware creates a number of ports for
connecting to a CompactFlash device. The core does not have any user selectable
options. Table XX lists the connections required from the CompactFlash core to
the CompactFlash device.
Table X CompactFlash Signals
Signal Pin Type Compact
Name Flash Pin
Number
addr[0] O 20
addr[1] O 19
addr[2] O 18
addr[3] O 17
addr[4] O 16
addr[5] O 15
addr[6] O 14
addr[7] O 12
addr[8] O 11
addr[9] O 10
addr[10] O 8
atasel_n O 9
cs_n[0] O 7
cs_n[1] O 32
data[0] I/O 21
data[1] I/O 22
data[2] I/O 23
data[3] I/O 2
data[4] I/O 3
data[5] I/O 4
data[6] I/O 5
data[7] I/O 6
data[8] I/O 47
data[9] I/O 48
data[10] I/O 49
data[11] I/O 27
data[12] I/O 28
data[13] I/O 29
data[14] I/O 30
data[15] I/O 31
detect I 25 or 26
intrq I 37
iord_n O 34
iordy I 42
iowr_n O 35
power O Compact
Flash
power
controller (if
present)
reset_n O 41
rfu O 44
we_n O 36
Software Programming Model
HAL System Library Support

Applications wishing to use the CompactFlash TrueIDE interface

(altera_avalon_cf) will use two sets of registers to control the attached
device. The first is the IDE task file (ATA) register set. The second
provides control of the interface to that device.

ATA registers

Provides access to the standard True IDE mode (ATA) registers of an

attached device. The DATA register is 16 bits, the others are 8 bit values.

Selecting the base (hardware) address and irq number:

#define ide_base <SOPC-name>_IDE_BASE

#define ide_irq <SOPC-name>_IDE_IRQ

Reading ATA registers:

IORD_ALTERA_AVALON_CF_IDE_DATA(ide_base)
IORD_ALTERA_AVALON_CF_IDE_ERROR(ide_base)
IORD_ALTERA_AVALON_CF_IDE_SECTOR_COUNT(ide_base)
IORD_ALTERA_AVALON_CF_IDE_SECTOR_NUMBER(ide_base)
IORD_ALTERA_AVALON_CF_IDE_CYLINDER_LOW(ide_base)
IORD_ALTERA_AVALON_CF_IDE_CYLINDER_HIGH(ide_base)
IORD_ALTERA_AVALON_CF_IDE_DEVICE_HEAD(ide_base)
IORD_ALTERA_AVALON_CF_IDE_STATUS(ide_base)
IORD_ALTERA_AVALON_CF_IDE_ALTERNATE_STATUS(ide_base)

Writing ATA registers:

IOWR_ALTERA_AVALON_CF_IDE_DATA(ide_base, data)
IOWR_ALTERA_AVALON_CF_IDE_FEATURES(ide_base, data)
IOWR_ALTERA_AVALON_CF_IDE_SECTOR_COUNT(ide_base, data)
IOWR_ALTERA_AVALON_CF_IDE_SECTOR_NUMBER(ide_base, data)
IOWR_ALTERA_AVALON_CF_IDE_CYLINDER_LOW(ide_base, data)
IOWR_ALTERA_AVALON_CF_IDE_CYLINDER_HIGH(ide_base, data)
IOWR_ALTERA_AVALON_CF_IDE_DEVICE_HEAD(ide_base, data)
IOWR_ALTERA_AVALON_CF_IDE_COMMAND(ide_base, data)
IOWR_ALTERA_AVALON_CF_IDE_DEVICE_CONTROL(ide_base, data)

Compact Flash interface control registers:

Provides the control of power, reset, insertion/removal detection, with

and interrupts.

Selecting the base (hardware) address and irq number:

 #define ctl_base <SOPC-name>_CTL_BASE
#define ctl_irq <SOPC-name>_CTL_IRQ

1) Interface control and status register:

Reading register:

IORD_ALTERA_AVALON_CF_CTL_STATUS(ctl_base)

Writing register:

IOWR_ALTERA_AVALON_CF_CTL_CONTROL(ctl_base, data)

bit definitions:

ALTERA_AVALON_CF_CTL_STATUS_PRESENT_MSK
ALTERA_AVALON_CF_CTL_STATUS_PRESENT_OFST

Relects the presence of a device (Compact Flash card).

If the bit is on, then the device is plugged in (present).

ALTERA_AVALON_CF_CTL_STATUS_IRQ_EN_MSK
ALTERA_AVALON_CF_CTL_STATUS_IRQ_EN_OFST

Enables interrupts for insertion or removal events. The PRESENT bit

will indicate which. The interrupt condition is cleared when the STATUS
register is read.

ALTERA_AVALON_CF_CTL_STATUS_POWER_MSK
ALTERA_AVALON_CF_CTL_STATUS_POWER_OFST

Controls power to the device. If asserted, the device will be powered up.

ALTERA_AVALON_CF_CTL_STATUS_RESET_MSK
ALTERA_AVALON_CF_CTL_STATUS_RESET_OFST

Controls the reset pin to the connected device. If asserted, the

connected device will be reset.

2) IDE interrupt control register

Allows the control of IDE device interrupts being propagated to

the host. The register is read/write.
 IOWR_ALTERA_AVALON_CF_IDE_CTL(ctl_base, data)
IORD_ALTERA_AVALON_CF_IDE_CTL(ctl_base)

Bit definitions:

ALTERA_AVALON_CF_IDE_CTL_IRQ_EN_MSK
ALTERA_AVALON_CF_IDE_CTL_IRQ_EN_OFST

When asserted, allows interrupts from IDE device operations to

interrupt the host.

Examples:

Enable IDE device interrupts

IOWR_ALTERA_AVALON_CF_IDE_CTL(ctl_base,
ALTERA_AVALON_CF_IDE_CTL_IRQ_EN_MSK)

Disable IDE device interrupts

IOWR_ALTERA_AVALON_CF_IDE_CTL(ctl_base, 0)

Software Files
The CompactFlash core is accompanied by the following software files. These
files provide low-level access to the hardware. Application developers should not
modify these files.
• altera_avalon_cf_regs.h – This file defines the core’s register map,
providing symbolic constants to access the low-level hardware. The
symbols in this file are used only by device driver functions.
• altera_avalon_cf.h, altera_avalon_cf.c – These files implement the
CompactFlash core device driver for the HAL system library.

Register Map
The CompactFlash core has two separate slave ports, each with an associated
register map. The ide port exposes to the user, the IDE register set found on the
CompactFlash device. Table X lists these IDE registers. A detailed description
of the register contents and functions can be found in the CF+ and CompactFlash
Specification available from the CompactFlash Association.
 CompactFlash Core ide Register Map
Off- Register Name
set Read Write
0 RD Data WR Data
1 Error Features
2 Sector Count Sector Count
3 Sector No. Sector No.
4 Cylinder Low Cylinder Low
5 Cylinder High Cylinder High
6 Select Card/Head Select Card/Head
7 Status Command
14 Alt Status Device Control

Table X shows the register map for the ctl slave port of the CompactFlash core.

CompactFlash Core ctl Register Map

Off- Register R/W Description/Register Bits
set Name 32 … 3 2 1 0
0 cfctl (2) R/W (1) idet rst pwr det
1 idectl R/W (1) iide
2 reserved RO (1)
3 reserved RO (1)
Notes
(1) These bits are reserved; they will always read as zero. Writing has no effect.
(2) Reading this register clears a detection interrupt.

cfctl Register
The cfctl register consists of individual bits, each controlling an aspect of the
CompactFlash core’s operation. The value in the cfctl register can be read at any
time.

The cfctl register bits are shown in table X.

 cfctl register bits
Bit Bit Read/W Description
Number Name rite
0 det RO Detect. The det bit indicates if the
CompactFlash core detects a
CompactFlash device. When the det bit
is 1, the core detects a CompactFlash
device. When the det bit is 0, no device
is detected.
1 pwr RW Power. The pwr bit allows an Avalon
master peripheral to control the power
supplied to a CompactFlash device.
Power is supplied to the device when
the pwr bit is set to 1. When the pwr bit
is 0, power is removed from the device.

2 rst RW Reset. The rst bit allows an Avalon

master peripheral to reset the
CompactFlash device. When the rst bit
is 1, the device is held in a reset state.
Setting this bit to 0 returns the device to
its active state.
3 idet RW Detect Interrupt Enable. When this bit is
1, the CompactFlash core generates an
interrupt when the det bit changes
(device removed or inserted). If the idet
bit is 0, no interrupt is generated.
Reading this register clears an interrupt
condition.

idectl Register
The idectl register consists of individual bits, each controlling an aspect of the
interface to the CompactFlash device. The value in the idectl register can be read
at any time.

The idectl register bits are shown in table X.

idectl register bits

Bit Bit Read/W Description
Number Name rite
0 iide RW IDE Interrupt Enable. When this bit is 1,
the CompactFlash core generates an
interrupt when the CompactFlash device
generates and interrupt. If the idet bit is
0, no interrupt is generated.
Interrupt Behavior
The CompactFlash core outputs two IRQ signals, one for each Avalon slave
interface. These can connect to any master in the system, such as a Nios II
processor.

The ctl port generates an interrupt when the det bit of the cfctl register changes,
indicating a CompactFlash device has been inserted or removed. Reading from
the cfctl register clears the interrupt condition. Generation of this interrupt can be
enabled or disabled with the idet bit of the cfctl register.

The ide port also generates an interrupt. It passes on interrupts generated by the
CompactFlash device. Information on CompactFlash interrupts can be found in
the CF+ and CompactFlash Specification. Generation of this interrupt can be
enabled or disabled with the xxx bit of the idectl register.