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1.1 Existing System: Design and Implementation of Four Bit Ripple Carry Adder Using 180Nm Cmos Technology
1.1 Existing System: Design and Implementation of Four Bit Ripple Carry Adder Using 180Nm Cmos Technology
1. INTRODUCTION
Most of the VLSI applications, such as digital signal processing, image and
video processing and microprocessors, extensively use arithmetic operations. Addition,
subtraction, multiplication and multiply and accumulate (MAC) are examples of the
most commonly used operations. The 1-bit full-adder cell is the building block of all
these modules. Thus, enhancing its performance is critical for enhancing the overall
module performance. The most important performance parameters for future VLSI
systems are speed and power consumption. this paper we present a novel 1-bit full adder
cell which offers faster operation and consumes less area and power than standard
implementations of the full adder cell.
With the popularity of portable systems as well as fast growth of power density
in integrated circuits, power dissipation becomes main design objectives equal for
digital system has become main goal. Generally ripple carry adders are used among all
types of adders because of its compact design but it is the slowest adder.
Several ripple carry adders have been proposed using different full adder cells
targeting on design accents such as power, delay and area. Among those designs with
less transistor count using transmission gate logic have been widely used to reduce area.
The proposed ripple carry adder is implemented using Cadence EDA too. The
tool provides sophisticated features such as Cadence Virtuoso Schematic Editor which
provides sophisticated capabilities which speed and ease the design, Cadence Virtuoso
Visualization and Analysis which efficiently analyzes the performance of the design and
Cadence Virtuoso Layout Suite that speeds up the physical layout of the design.
In this paper, we propose a design of ripple carry adder using full adder cell with
18 transistors. The paper is organized as follows: in section II, previous work is
reviewed. Subsequently, in section III, the proposed design of ripple carry adder is
presented. In section IV, the schematic and layout of the adders are presented. In section
V, the simulation results are given and discussed. The comparison and evaluation for
proposed and conventional designs are carried out. Finally a conclusion will be made in
the last section
Department of ECE,NNRG 1
DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
outputs, a sum and a carry; this circuit is called a full adder. The relation between the
inputs A, B, Cin and the outputs Sum and Cout are expressed as:
Inputs Outputs
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Department of ECE,NNRG 2
DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
The conventional full adder shown in Fig 1.1 is a complementary CMOS (C-
CMOS) full adder with 28 transistors. It is a combination of PMOS pull up transistors
and NMOS pull down transistors. It is well known for its robustness and scalability at
low supply voltages. The complementary CMOS logic circuit has the advantages of
layout regularity and stability at low voltage due to the complementary transistor pairs
and smaller number of interconnecting wires. But its power consumption and transistor
count are relatively high for low power arithmetic circuits. In this full adder,
interdependence between signals generation (SUM signal relies on the generation of
COUT signal) causes the problem of delay imbalance.
Ripple carry adder is built using multiple full adders such as the above discussed
conventional full adder. In ripple carry adder each carry bit from a full adder "ripples"
to the next full adder. The simple implementation of 4-bit ripple carry adder is shown
below. C0 is the input carry, x0 through x3 and y0 through y3 represents two 4-bit input
binary numbers.
Department of ECE,NNRG 3
DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
The proposed ripple carry adder is designed using a full adder cell with 18-
transisitors based on transmission gate. It uses a novel exclusive-or (XOR) gate. The
schematic for this XOR gate is shown in Fig.1.3.
Department of ECE,NNRG 4
DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
1.3PROBLEM DEFINITION
The issue of case of design is not always attained easily. The CMOS design style
is not area efficient from complex gates with large fan-in's in conventional ripple carry
adder. The power consumption and transistor count are relatively high for low power
Arithmetic circuits. To overcome this problem we reduce the transistor count, delay and
power.
Department of ECE,NNRG 5
DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
1.7 ORGANIZATIONOFTHESIS
This is report contains six chapters.
CHAPTER 1: Introduction about the Project.
CHAPTER 2: Literature Survey introduction to VLSI.
CHAPTER 3: Hardware Description.
CHAPTER 4: Software Description.
CHAPTER 5: Results.
CHAPTER 6: Conclusion and Future Scope.
2 . LITERATURE SURVEY
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
new state-of-the-art digital camera, the cell-phones, and what have you. All this
involves a lot of expertise on many fronts within the same field.
VLSI has been around for a long time, there is nothing new about it ... but as a
side effect of advances in the world of computers, there has been a dramatic
proliferation of tools that can be used to design VLSI circuits. Alongside, obeying
Moore's law, the capability of an IC has increased exponentially over the years, in terms
of computation power, utilisation of available area, yield. The combined effect of these
two advances is that people can now put diverse functionality into the IC's, opening up
new frontiers. Examples are embedded systems, where intelligent devices are put inside
everyday objects, and ubiquitous computing where small computing devices proliferate
to such an extent that even the shoes you wear may actually do something useful like
monitoring your heartbeats! These two fields are kind of related, and getting into their
description can easily lead to another article.
The invention of the transistor by William B. Shockley, Walter H. Brattain and
John Bardeen of Bell Telephone Laboratories drastically changed the electronics
industry and paved the way for the development of the Integrated Circuit (IC)
technology. The first IC was designed by Jack Kilby at Texas Instruments at the
beginning of 1960 and since that time there have already been four generations of ICs
.Viz SSI (small scale integration), MSI (medium scale integration), LSI (large scale
integration), and VLSI (very large scale integration). Now were ready to see the
emergence of the fifth generation, ULSI (ultra large scale integration) which is
characterized by complexities in excess of 3 million devices on a single IC chip. Further
miniaturization is still to come and more revolutionary advances in the application of
this technology must inevitably occur.
Over the past several years, Silicon CMOS technology has become the dominant
fabrication process for relatively high performance and cost effective VLSI circuits. The
revolutionary nature of this development is understood by the rapid growth in which the
number of transistors integrated in circuits on a single chip.
Department of ECE,NNRG 7
DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
With the small transistor at their hands, electrical engineers of the 1950s saw the
possibilities of constructing far more advanced circuits. As the complexity of circuits
grew, problems arose.
One problem was the size of the circuit. A complex circuit, like a computer, was
dependent on speed. If the components of the computer were too large or the wires
interconnecting them too long, the electric signals couldn't travel fast enough through
the circuit, thus making the computer too slow to be effective.
Jack Kilby at Texas Instruments found a solution to this problem in 1958.
Kilby's idea was to make all the components and the chip out of the same block
(monolith) of semiconductor material. Kilby presented his idea to his superiors, and was
allowed to build a test version of his circuit. In September 1958, he had his first
integrated circuit ready. Although the first integrated circuit was crude and had some
problems, the idea was groundbreaking. By making all the parts out of the same block
of material and adding the metal needed to connect them as a layer on top of it, there
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
was no need for discrete components. No more wires and components had to be
assembled manually. The circuits could be made smaller, and the manufacturing process
could be automated. From here, the idea of integrating all components on a single
silicon wafer came into existence, which led to development in small-scale integration
(SSI) in the early 1960s, medium-scale integration (MSI) in the late 1960s, and then
large-scale integration (LSI) as well as VLSI in the 1970s and 1980s, with tens of
thousands of transistors on a single chip (later hundreds of thousands, then millions, and
now billions (109)).
2.3 Developments
The first semiconductor chips held two transistors each. Subsequent advances
added more transistors, and as a consequence, more individual functions or systems
were integrated over time. The first integrated circuits held only a few devices, perhaps
as many as ten diodes, transistors, resistors and capacitors, making it possible to
fabricate one or more logic gates on a single device. Now known retrospectively as
small-scale integration (SSI), improvements in technique led to devices with hundreds
of logic gates, known as medium-scaleintegration (MSI). Further improvements led to
large-scale integration (LSI), i.e. systems with at least a thousand logic gates. Current
technology has moved far past this mark and today's microprocessors have many
millions of gates and billions of individual transistors.
At one time, there was an effort to name and calibrate various levels of large-
scale integration above VLSI. Terms like ultra-large-scale integration(ULSI) were used.
But the huge number of gates and transistors available on common devices has rendered
such fine distinctions moot. Terms suggesting greater than VLSI levels of integration
are no longer in widespread use.
As of early 2008, billion-transistor processors are commercially available. This
became more commonplace as semiconductor fabrication advanced from the then-
current generation of 65 nm processes. Current designs, unlike the earliest devices, use
extensive design automation and automated logic synthesis to lay out the transistors,
enabling higher levels of complexity in the resulting logic functionality. Certain high-
performance logic blocks like the SRAM (static random-access memory) cell, are still
designed by hand to ensure the highest efficiency. VLSI technology may be moving
toward further radical miniaturization with introduction of NEMS technology.1970s -
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
NMOS Technology – Intel 1101 SRAM – 256 bit static random access memory and
4004 4-bit microprocessor
Late 40s Transistor invented at Bell Labs
Late 50s First IC (JK-FF by Jack Kilby at TI)
Early 60s Small Scale Integration (SSI) 10s of transistors on a chip
Late 60s Medium Scale Integration (MSI) 100s of transistors on a chip
Early 70s Large Scale Integration (LSI) 1000s of transistor on a chip
Early 80s VLSI 10,000s of transistors on a chip (later 100,000s & now 1,000,000s)
Ultra LSI is sometimes used for 1,000,000s.Research has a long history of
involvement with IBM high-performance processor design: from the pioneering 801
RISC processor of the 1980s and ground-breaking work in Very Long Instruction Word
(VLIW) architecture and systems to the first IBM mainframe with a CMOS
microprocessor in 1996 and the current ultra-complex systems such as those use
POWER5™. As the latest processor for IBM’s I Series™ and p Series® systems,
POWER5 uses eight levels of copper wiring and over a quarter billion transistors to take
full advantage of IBM’s leading-edge 130 nm. Silicon-On-Insulator (SOI) technology.
Research continues to make major contributions to IBM’s microprocessors, spanning
the full spectrum of system design, including micro architectures, circuits and circuit
techniques, low power, design methodologies and tools, design verification, and
interaction with technology development. A strong focus centers on developing
advanced high-end systems. Along with industry collaborators, for example, Research is
working with IBM’s Systems and Technology Group in the development of future
server processors, as well as the Cell Broadband Engine™ — the next generation of
scalable and power-efficient microprocessors, a multi-core architecture optimized for
computer-intensive rich media applications. IBM places a significant emphasis on
System-on-a-Chip (SoC) design capabilities, in which pre-design components are used
to quickly compose chips with high levels of function. Research contributes to IBM’s
SoC capabilities in both the design and tools areas. These capabilities played an integral
part in the design of Blue Gene/L that became the world’s fastest supercomputer in
2004.
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
that the earlier CPUs on the market had a single speed or frequency rating while the
newer models have a rating which refers to more than one CPU.
2.7 VLSI DESIGN FLOW
The VLSI IC circuits design flow is shown in the figure below. The various
level of design are numbered and the gray coloured blocks show processes in the design
flow
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
The first mask defines the n-well regions. This is followed by a low dose
phosphorus implant driven in by a high temperature diffusion step to form the n-wells.
The well depth is optimized to ensure against-substrate top+ diffusion breakdown
without compromising then-wellton+ mask separation. The next steps are to define the
devices and diffusion paths, grow field oxide, deposit and pattern the polysilicon, carry
out the diffusions, make contact cuts, and finally metalize as before. lt will be seen that
an n+ mask and its complement may be used to define the n- and p-diffusion regions
respectively. These same masks also include the VDDandVsscontacts(respectively). It
should be noted that, alternatively, we could have used a p+ mask and its complement.
Since the n+ and p+ masks are generally complementary.
Integration's aim is to cover every aspect of the VLSI area, with an emphasis on
cross-fertilization between various fields of science, and the design, verification, test
and applications of integrated circuits and systems, as well as closely related topics in
process and device technologies.
Design entry: It describes the RTL (Register Transfer Level) logics in HDLs.
For this, we use any of the hardware description languages (HDLs) such as verilog and
VHDL. This design specification contains all the details which all are required for the
design architecture, RTL block diagram, clock frequency, frequency domain details,
waveforms, port details etc.
Logic Synthesis: The RTL logic written is synthesized to get the gate level net
list. This process can be done with the help of EDA tools. The code written can be
implemented on an FPGA board only if, it is synthesizable.
Gate level simulation: The gate level simulation of the logic is very important
in the verification. The functional check, timing checks and the Power analysis checks
are included in the verification.
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
As we all know VLSI stands for Very large scale integration. Very large scale
integration is the process of creating an integrated circuit by combining thousands of
transistors into a single chip. Now the question comes why we need VLSI. So the
answer is that one of the most characteristics of information service is there increasing
need for very high processing and band width. The other important characteristics is that
the information service tend to become more personalized, which means that the
information processing device must be more intelligent and also be portable to allow
more mobility.
VLSI is mainly classified in two classes.
VLSI back end – VLSI back-end includes Route, place and floor planning.
Back end includes development and fabrication part. It is too costly and time consuming
process. Physical designing and layout refers to back end.
VLSI front end – VLSI Frontend includes designing and testing part. It uses
Verilog and HDL, VHDL .RTL designing, minimizing delay and simulation refers to
Front end.
There are two important steps. VLSI design and design verification. VLSI
design refers to the designing of VLSI circuits and its implementation. Design
verification is use to test the design and verify us that the given designing is working
properly or not
Now, we should move towards physical and digital design of VLSI. Both are
very important part of VLSI. Digital design is divided in three steps. First is, second is
structural and third one is design. Behavioural describes the algorithm, structural
describes component and their connections, and physical describes how circuit built.
Department of ECE,NNRG 16
DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
In standard design cycle physical design comes after the circuit design. Physical design
includes both design and verification and validation of layout. At this step circuit
representation is converted into geometric representation.
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
phones and personal digital assistants are gaining prominence. For these systems, low
power consumption is a prime concern, because it directly affects the performance by
having effects on battery longevity. In this situation, low power VLSI design has
assumed great importance as an active and rapidly developing field.
At the circuit design level, considerable potential for power savings exists by
means of proper choice of a logic style for implementing combinational circuits. This is
because all the important parameters governing power dissipation switching
capacitance, transition activity, and Short-circuit currents are strongly influenced by the
chosen logic style.
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
should be robust against transistor downsizing, i.e., correct functioning of logic gates
with minimal or near minimal transistor sizes must be guaranteed.
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
The area demonstrates the CMOS transistor, its design, static qualities and
dynamic characteristics. The vertical piece of the device and the three-dimensional
layout of the products are in like manner portrayed.
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
2.12 CMOS
Complementary metal oxide semiconductor, abbreviated as CMOS, is a
development for building coordinated circuits. CMOS innovation is utilized as a part of
a chip, microcontrollers, static RAM, and other propelled method of reasoning circuits.
CMOS development is similarly used for a couple of basic circuits, for instance, picture
sensors, data converter, and extremely consolidated handsets for a few sorts of
correspondence. In the year 1963, Frank Wanlass who was working for Fairchild
Semiconductor, authorized CMOS. CMOS is suggested as correlative symmetry metal-
oxide-semiconductor or COS-MOS from time to time.
CMOS is moreover from time to time suggested as correlative symmetry metal-
oxide-semiconductor or COS-MOS. The words “comparing symmetry” suggest the way
that the ordinary arrangement style with CMOS uses correlative and symmetrical
arrangement of p-sort and n-sort metal oxide semiconductor field effect transistors i.e.,
MOSFET’s for justification limits.
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
was essentially thus that CMOS turned into the most utilized innovation to be executed
in VLSI chips.
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
3 SOFTWARE DESCRIPTIONS
3.1 Tools Used
The tools used in the thesis are as follows:
Simulation Software:
Cadence EDA Tool
3.1.1 Boolean Algebra
Boolean algebra is the field of mathematics that deals exclusively with the set of
values consisting of True and False [8]. It is the mathematical foundation for all digital
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
electronics, and a review of this subject is absolutely necessary to understand the design
of the adder. In addition, we will see how Boolean algebra provides useful abstractions
for the construction of virtually any type of digital circuit.
Table:3.1.2
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
A B C OUT
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 0
Table : 3.1.3 An Example Truth Table.
This truth table has a range of input combinations, only three of which output 1. We
can write this mathematically using the following notation:
OUT = A • B • C + A • B • (7 + A- B- CJ.
In this expression, the symbol refers to the logical OR operation, while the
“ s ym b o l is the AND operation. It is very convenient to write out truth tables as
combinations of these operations, because the AND and OR operations are
commutative, associative, and distributive over each other [8] (a more complete list of
the properties of logical operations is provided in Appendix II). This means that OUT
could be written many different ways,including the following:
OUT = A • B • C + A • B . (7 + A- i? - CJ =A • (B • C + B • C) + A • B • C = A . B . C
+ C 7 ( A . B + A . B ) =etc.
The properties of these logical operations make them extraordinarily useful to
physicists and engineers, as it gives them the flexibility to choose between many
possible implementations of the same function (some of which may be much easier than
others to actually build). To see this, let us look at the example of the XOR gate.
Example: The XOR Gate
The XOR gate, also called the “exclusive-OR gate”,is a modified version of the
OR gate, in which the output is 1 if A or B is 1, but 0 if both A and B are 1. Its truth
table is given below, and at first glance it does not seem much more complex than any
of the gates listed above; however, it is deceptively challenging to actually implement
using discrete transistors. As an exercise, let us apply some of the principles of Boolean
algebra to implement the XOR gate as a combination of simpler logical opera tions.
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
A B A㊉B
0 0 0
0 1 1
1 0 1
1 1 0
Table 3.1.4
A ㊉B = A • B + A • B.
By the Complementation and Identity over OR Laws (see Appendix II), I can also
add the following terms without changing the output:
A ㊉B = B • A + A • B + A • A + B • B.
OR)
=(A + B) • (B+ A)(Distributive over AND)
=(A + B) • (A • B)(De Morgan’s Law)
This result is something that can be easily implemented. It consists of an OR
operation, a NAND operation, and then performs an AND on the two results. Hence, the
XOR gate can be implemented in the following way:
Department of ECE,NNRG 28
DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
This is a very simple example of how the principles of Boolean algebra can be used
to design a digital circuit from logical operators. Although addition is a more
complicated operation than XOR, the ideas and techniques illustrated here will translate
over to the design of the adder very nicely
Example: Implementation of the NAND gate using MOSFET,s
Fig3.1.5: Implementation of the NAND gate using two n-type MOSFET’s. This circuit
has inputs A and B, and an output A- B.
So far in this section, I have discussed how logical operations can be used to
construct digital components, but how can transistors be used to implement these logical
operations in the first place? For example, consider the NAND gate, which has an
output of 0 if both of its inputs are 1, and an output of 1 otherwise (refer to Table I for
the full truth table). This function can be created by attaching two n-type MOSFET’s in
series, with one transistor’s source terminal attached to the other’s drain terminal (see
Figure 5). The output of such a circuit would be 0 if both A and B were 1, because both
transistors would be allowing current to pass through directly to ground. If only one (or
neither) transistor were on, then the output would have to be high.
There were some design choices made in Figure 5. For one, the values of the
voltage source and the pull-up resistor are arbitrary, depending on what output current is
desired. Also, Figure 5 does not represent the only possible implementation of the
NAND gate. There are many possible variations, some of which may be more elegant
than the one pictured above. However, it is the opinion of this author that Figure 5
represents the simplest implementation of the NAND gate that is to be constructed using
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
between -128 and 127. Suppose we want to use our device to add 120 and 9. Both are
valid integers under this architecture, but their sum of 129 is not. A conscientious user
will be aware of this limitation and take steps to avoid it during use, but finding a way
to alert the user that overflow has occurred will be an important part in the design of the
adder.
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
G G
A B in SUM out
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Gout are also 1. From these rules a truth table for the adder can be produced, which is
given on Table 4.
Table 4 provides the basis from which a 1-bit adder can be constructed. Generally
speaking, however, merely adding one bit to another bit is not that interesting. Much
more interesting would be creating a circuit that could compute the above example,
which contained two 8-bit inputs. This is entirely possible to do, since the operation is
exactly the same for each pair of bits. All that we need to do is design multiple 1-bit
adders from Table 4, and connect them in series such that Gout from the first pair of bits
is Gin for the second pair, and so on. This serialization of 1-bit adders through the carry-
out is the defining feature of the “ripple-carry” adder.
=
Cin㊉(A ㊉B)(Definition of XOR)
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
This last equation is something that can be easily implemented using two XOR
gates, which w
C
out = A • B • Cin+ A • B • C+ A • B • Cin+ A • B • Cin
= C i n • (A • B + A • B) + (A • B) • (Cin+ Cin) (Distributive over OR)
Complementation Law)
This result for Cout is simple enough to implement, especially since I already have
an XOR gate that compares A and B for the sum. I can reuse the output for that gate to
reduce the number of total gates in the adder like so:
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
Fig: 3.2.2 The complete full-bit adder. Note that the multi-colored
wires indicate that there is no junction where they cross.
Figure 7 represents the complete 1-bit adder, which I can implement and duplicate
four times to make a 4-bit, ripple carry adder.
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
last and next- to-last carry-outs. If the result is 1, then there has been overflow. If it is 0,
the sum is valid. This XOR gate is visualized in its appropriate place in Figure 9, and
will be implemented during the construction of the adder.
Table:3.3.1
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
out. A one-bit full adder adds three one-bit numbers, often written as A, B and Cin; A and
B are the operands, and Cin is a bit carried in from the previous less significant stage.
The Full adder is usually a component in a cascade of adders, which add 8,16, 32, etc.
bit binary numbers. The circuit produces a two-bit output, output carry and sum.
Whereas the equation of the sum and carry is
S=AXORB ;------------------------------------------(1)
Cout=AANDB ; --------------------------------------------(2)
Fig3.3.2schematicdiagramoffulladder
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
Notices that both propagate and generate signals depend only on the input bits and thus
will be valid after one gate delay.
The new expressions for the output sum and the carryout are given by
Si= Pi⊕ Ci-1
C = G+ PC
i+1 i i
These equations show that a carry signal will be generated in two cases:
1) if both bits Aiand Biare 1
C =G +P C =G +P G +P P G +P P P C
3 2 2 2 2 2 1 2 1 0 2 1 0 0
These expressions show that C2, C3 and C4 do not depend on its previous carry-in.
Therefore C4 does not need to wait for C3 to propagate. As soon as C0 is computed, C4
can reach steady state. The same is also true for C2 and C3
Department of ECE,NNRG 40
DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
This is a two level circuit. In CMOS however the delay of the function is non linearly
dependent on its fan in. Therefore large fan in gates are not practical.
Carry look-ahead adder’s structure can be divided into three parts: the
propagate/generate generator Fig.1, the sum generator Fig. 2 and the carry generator
Fig.
Department of ECE,NNRG 41
DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY
4 SOFTWARE DESCRIPTION
4.1 Introduction
The intentions for this manual is to serve as an introduction to the Cadence de-
sign environment and describe the methodology used when designing integrated
circuits.
The department is not giving courses in Cadence but in integrated circuit design
so only the minimum knowledge, needed to run the laboratories, of Cadence can be
gained from this manual. Also this manual describes the environment currently at the
department which is Cadence version 4.45 in conjunction witch a Design Kit from AMS
(Austria Mikro System International AG) which contains a set of rules and designs for a
0.35 µm CMOS process.
For a more thorough understanding of Cadence the extensive on line manual set
is recommended. These are accessed from any of the tools by pressing the help button.
More information about the topics in the first two chapters can be found in the
manuals Design Framework II Help and Cadence Application Infrastructure User
Guide.
The Cadence tool kit consists of several programs for different applications such
as schematic drawing, layout, verification, and simulation. These applications can be
used on various computer platforms. The open architecture also allows for integration of
tools from other vendors or of own design. The integration of all this tools is done by a
program called Design Framework II (DFW).
The DFW-application is the cornerstone in the Cadence environment. It provides
a common user interface and a common data base to the tools used. This makes it
possible to switch between different applications without having to convert the data
base.
In a terminal window, sort csh at the summon provoke to conjure the C shell.
Csh
Source cshrc
If the "What's New..." window appears close it with the File Close command.
ECE Department NNRGIES 47
DESIGN AND IMPLEMENTATION OF RIPPLE CARRY ADDER IN 180NM CMOS TECHNOLOGY
Keep opened CIW window.
2. Try not to alter the Library way document and the one above may be not quite the
same as the way appeared in your frame.
3. Snap OK when done the above settings. A clear schematic window for the inverter
configuration shows up.
On the off chance that you put a segment with a wrong parameter esteems,
utilize the Edit Properties Objects charge the parameters.
Utilize the Edit Move order on the off chance that you put parts in the wrong
area.
5 SIMULATION
The reproduction device is begun straightforwardly from the schematic proof
reader and all the fundamental net records portraying the plan will be made. A
reproduction is normally preformed in a test seat, which is likewise a schematic, with a
genuine outline included as a case. The test seat additionally incorporates flag source
and power supply. By using parameters for the properties of the parts utilized it is
conceivable to rapidly breakdown the outline for an extensive variety of factors.
The test systems keep running from inside Affirma Analog Circuit Design
Environment which are an instrument that handles the interface between the client and
the test system. The present form of Cadence utilized at the office (4.45) utilizes the
AffirmaSpecter Circuit Simulator. The test system offers an extensive variety of
investigations (DC, recurrence clear, transient, clamor, and so on.) and be introduced
graphically and be spared.
The outcomes (voltage levels, streams, clamor, and so forth.) can be
bolstered into a mini-computer which can exhibit different parameter of the investigated
circuit – postpone time, rise time, slew rate, stage edge, and numerous other fascinating
properties. It is likewise conceivable to set up the logarithmic articulation of in or yield
flag which can be pointed as an element of some other variable.
In this segment, we will run the reenactment for Inverter and plot the transient ,
DC attributes and we will do Parametric Analysis after the underlying reenactment.
6. RESULTS
1. Conventional full adder designed by using cadence