204 TRANSMISSION LINES AND SIGNAL INTEGRITY

For a glass epoxy board with a wide conductor w ¼ 200 mils, and h ¼ 62 mils we
obtain from (4.43a) ZC ¼ 41:05 V. For coplanar strips with w ¼ 200 mils,
s ¼ 62 mils, and h ¼ 62 mils we compute from (4.42a) ZC ¼ 155:7 V. This illus-
trates the point that pairs of wide lands placed on opposite sides of the board will
give characteristic impedances lower than placing the lands on the same side of
the board (and using a spacing equal to the board width). Low-impedance power dis-
tribution circuits can be obtained in this fashion. Power distribution requires lines
having low inductance but high capacitance in order to reduce the effect of the
L di=dt voltage drops caused by sudden changes in the supply current. These
voltage drops along the distribution line lower the dc voltages at the modules
from, for example,
pffiffiffiffiffiffi5 V, possibly causing logic errors. Since the characteristic impe-
dance is ZC ¼ l=c, a low ZC indicates low inductance and/or high capacitance.
Hence dc power is often supplied by lands on opposite sides of a substrate
(perhaps a substrate different from that of the PCB).

4.3 THE TIME-DOMAIN SOLUTION

The time-domain solution of the transmission-line equations refers to the complete

solution of those equations with no assumptions as to the time form of the line
excitation. The other solution of interest is the sinusoidal steady-state or fre-
quency-domain solution considered in a later section, where the time form of the
line excitation is restricted to being sinusoidal and furthermore the sinusoidal
source is assumed to have been attached a sufficient length of time so that the
transients have decayed to zero, leaving the steady-state solution. The time-
domain solution is often referred to as being the “transient solution,” which is a mis-
nomer since the time-domain solution gives the total solution—transient plus steady
state. We will first investigate a graphical method of sketching the terminal voltages
of the line versus time. This gives considerable insight into what causes the overall
waveform shape. Next we will investigate the possibility of using the SPICE
(PSPICE) circuit analysis program to perform this computation. The SPICE
(PSPICE) program does not provide the insight that the graphical method provides,
but it allows the analysis of lines having dynamic as well as nonlinear terminations
for which the graphical method would be tedious.

4.3.1 Graphical Solutions

The transmission-line equations governing lossless lines are given in coupled, first-
order form in (4.2) and in uncoupled, second-order form in (4.3).
The solutions of the uncoupled, second-order form are [1,2]

 z  z
V(z, t) ¼ V þ t  þ V  t þ (4:44a)
v v
1 þ  z 1  z
I(z, t) ¼ V t   V t þ (4:44b)
ZC v ZC v
 4.3 THE TIME-DOMAIN SOLUTION 205

where ZC is the characteristic impedance of the line:

rffiffiffi
l
ZC ¼
c
¼ vl
1
¼ (4:45a)
vc

The characteristic impedance, ZC , is a real (not complex) number. Hence it would

be more properly called the characteristic resistance. The word “impedance” is a
frequency-domain (phasor) term, but here the source voltage waveform is not
necessarily a single-frequency sinusoid but may have an arbitrary waveform.
However, it has become an industry standard to refer to ZC as the characteristic
impedance, as we will continue to do here.
The velocity of propagation on the line is

1
v ¼ pffiffiffiffi
lc
1
¼ pffiffiffiffiffiffi (4:45b)
me

where the medium surrounding the conductors is characterized by m and e. These

results apply to lines in an inhomogeneous medium, where we would use e ¼
e0 e0r and e0r is the effective dielectric constant. The general forms of the solution
given in (4.44) are in terms of the functions V þ (t  z=v) and V  (t þ z=v). The
precise forms of these functions will be determined by the functional time-
domain form of the excitation source, VS (t). Nevertheless, they show that time
and position must be related as t  z=v and the t þ z=v in these forms. The function
V þ represents a forward-traveling wave traveling in the þz direction. This is clear,
since as time increases, z must also increase to keep the argument of the
function constant; that is, in order to track the movement of a point on the wave.
Similarly, the function V 2 represents a backward-traveling wave traveling in the
2z direction on the line. Thus the total solution consists of the sum of forward-
traveling and backward-traveling waves. The current of each wave is related to
the voltage of that wave by the characteristic impedance:

 z 1 þ z
Iþ t  ¼ V t (4:46a)
v ZC v
 z 1  z
I t þ ¼  V t þ (4:46b)
v ZC v
206 TRANSMISSION LINES AND SIGNAL INTEGRITY

We will consider lines of total length L. The forward- and backward-

traveling waves are related at the load, z ¼ L, by the load reflection coefficient
as [1,2]

V  (t þ L=v)
GL ¼
V þ (t  L=v)
RL  Z C
¼ (4:47)
RL þ Z C

Therefore the reflected waveform at the load can be found from the incident
wave using the reflection coefficient as

   
 L þ L
V tþ ¼ GL V t  (4:48)
v v

The reflection coefficient given in (4.47) applies to voltages only. A current

reflection coefficient can be derived by substituting (4.47) into (4.46), so that

   
L L
I t þ ¼ GL I þ t  (4:49)
v v

Observe that the current reflection coefficient is the negative of the voltage
reflection coefficient.
This reflection of waves at the load discontinuity is illustrated in Fig. 4.13. The
reflection process can be viewed as a mirror that produces, as a reflected V  , a
replica of V þ that is “flipped around,” and all points on the V  waveform are the
corresponding points on the V þ waveform multiplied by GL . Note that the total
voltage at the load, V(L, t), is the sum of the individual waves present at the load
at a particular time as shown by (4.44).
Now let us consider the portion of the line at the source, z ¼ 0, shown
in Fig. 4.14. When we initially connect the source to the line, we reason that a
forward-traveling wave will be propagated down the line. We would not expect a
backward-traveling wave to appear on the line until this initial forward-traveling
wave has reached the load, a time delay of TD ¼ L=v, since the incident wave
will not have arrived to produce this reflected wave. The portion of the incident
wave that is reflected at the load will require an additional time TD to move back
to the source at z ¼ 0. Therefore, for 0  t  2L=v, no backward-traveling
waves will appear at z ¼ 0, and for any time less than 2TD the total voltage
and current at z ¼ 0 will consist only of forward-traveling waves, V þ and I þ .
 4.3 THE TIME-DOMAIN SOLUTION 207

FIGURE 4.13 Reflection of waves at a termination.

Therefore
 
þ 0
V(0, t) ¼ V t  (4:50a)
v
 
þ 0
I(0, t) ¼ I t 
v
V þ (t  0=v) 2L
¼ for 0  t  (4:50b)
ZC v

Since the ratio of the total voltage and total current on the line is ZC for
0  t  2L=v, as shown in (4.50), the line appears to have an input resistance of
208 TRANSMISSION LINES AND SIGNAL INTEGRITY

FIGURE 4.14 The equivalent circuit seen at the input to a line before the wave reflected at
the load arrives.

ZC over this time interval, as shown in Fig. 4.14b. Thus the forward-traveling
voltage and current waves that are initially launched are related to the source
voltage by (use voltage division)

ZC
V(0, t) ¼ VS (t) (4:51a)
RS þ Z C
VS (t)
I(0, t) ¼ (4:51b)
RS þ Z C

The initially launched waves have the same shape as the source voltage.
The initially launched wave travels toward the load, requiring a time TD ¼ L=v
for the leading edge of the pulse to reach the load. When the pulse reaches the load, a
reflected pulse is initiated, as shown in Fig. 4.13. This reflected pulse requires an
additional time TD ¼ L=v for its leading edge to reach the source. At the source
we can obtain a voltage reflection coefficient

R S  ZC
GS ¼ (4:52)
R S þ ZC
 4.3 THE TIME-DOMAIN SOLUTION 209

as the ratio of the incoming incident wave (which is the reflected wave at the load)
and the reflected portion of this incoming wave (which is sent back toward the load).
A forward-traveling wave is therefore initiated at the source in the same fashion as at
the load. This forward-traveling wave has the same shape as the incoming back-
ward-traveling wave (which is the original pulse sent out by the source and reflected
at the load), but corresponding points on the incoming wave are reduced by GS . This
process of repeated reflections continue as re-reflections at the source and load. At
any time, the total voltage (current) at any point on the line is the sum of all the indi-
vidual voltage (current) waves existing on the line at that point and time, as is shown
by (4.44).

Review Exercise 4.7 Determine the characteristic impedances and velocities of

propagation for the wire-type lines in Review Exercises 4.1– 4.3

Answers: 225 V, 3  108 m=s; 234 V, 3  108 m=s; 51 V, 1:98  108 m=s.
Review Exercise 4.8 Determine the characteristic impedances and velocities of
propagation of the rectangular cross-section lines in Review Exercises 4.4– 4.6.

Answers: 63:8 V, 1:38  108 m=s; 151 V, 1:72  108 m=s; 144:45 V, 1:8  108 m=s.

Example 4.1 As an example, consider the transmission line shown in Fig. 4.15a.
At t ¼ 0 a 30-V battery with zero source resistance is attached to the line, which has
a total length of L ¼ 400 m, a velocity of propagation of v ¼ 200 m=ms, and a
characteristic impedance of ZC ¼ 50 V. The line is terminated in a 100-V resistor,
so that the load reflection coefficient is

100  50
GL ¼
100 þ 50
1
¼
3
and the source reflection coefficient is

0  50
GS ¼
0 þ 50
¼ 1

The one-way transit time is TD ¼ L=v ¼ 2 ms. At t ¼ 0 a 30-V pulse is sent down
the line, and the line voltage is zero prior to the arrival of the pulse and 30 V after the
pulse has passed. At t ¼ 2 ms the pulse has arrived at the load, and a backward-
traveling pulse of magnitude 30GL ¼ 10 V is sent back toward the source. When
this reflected pulse arrives at the source, a pulse of magnitude GS of the incoming
pulse or GS GL 30 ¼ 10 V is sent back toward the load. This pulse travels to the
load, at which time a reflected pulse of GL of this incoming pulse or GL GS GL 30 ¼
210 TRANSMISSION LINES AND SIGNAL INTEGRITY

FIGURE 4.15 An example to illustrate sketching the voltage on a line as a function of

position, Example 4.1.
 4.3 THE TIME-DOMAIN SOLUTION 211

3:33 V is sent back toward the source. At each point on the line the total line
voltage is the sum of the waves present on the line at that point.

Example 4.2 The previous example has illustrated the process of sketching the
line voltage at various points along the line and at discrete times. Generally we
are interested only in the voltage at the source and load ends of the line, V(0, t)
and V(L, t), as continuous functions of time. In order to illustrate this process, let
us reconsider the previous example and sketch the voltage at the line output,
z ¼ L, as a function of time, as is illustrated in Fig. 4.16. At t ¼ 0 a 30-V pulse
is sent out by the source. The leading edge of this pulse arrives at the load at
t ¼ 2 ms. At this time a pulse of GL 30 ¼ 10 V is sent back toward the source.
This 10-V pulse arrives at the source at t ¼ 4 ms, and a pulse of GS GL 30 ¼ 10 V
is returned to the load. This pulse arrives at the load at t ¼ 6 ms, and a pulse of
GL GS GL 30 ¼ 3:33 V is sent back toward the source. The contributions of these
waves at z ¼ L are shown in Fig. 4.16 as dashed lines, and the total voltage is
shown as a solid line. Note that the load voltage oscillates during the transient
time interval about 30 V, but asymptotically converges to the expected steady-
state value of 30 V. If we had attached an oscilloscope across the load to display
this voltage as a function of time, and the timescale were set to 1 ms per division,
it would appear that the load voltage immediately assumed a value of 30 V. We
would see the picture in Fig. 4.16 including the transient time interval only if the
time scale of the oscilloscope were sufficiently reduced to, say, 1 ms per division.
In order to sketch the load current I(L, t), we could divide the previously sketched
load voltage by RL . We could also sketch this directly by using current reflection
coefficients GS ¼ 1 and GL ¼ 13 and an initial current pulse of 30 V=ZC ¼ 0:6 A.
The current at the input to the line is sketched in this fashion in Fig. 4.16c.
Observe that this current oscillates about an expected steady-state value of
30 V=RL ¼ 0:3 A.

Example 4.3 This example shows the effect of pulsewidth on the total voltages.
Consider a line of length 0.2 m (7.9 in.) shown in Fig. 4.17a. The source voltage
is a pulse of 20 V amplitude and 1 ns duration. The line has a characteristic impe-
dance of 100 V and a velocity of propagation of 2  108 m=s. The source resistance
is 300 V (RS ¼ 300 V) and the load is open-circuited (RL ¼ 1). Sketch the voltage
at the input to the line and at the load.

Solution: The source reflection coefficient is

300  100
GS ¼
300 þ 100
1
¼
2
212 TRANSMISSION LINES AND SIGNAL INTEGRITY

FIGURE 4.16 An example to illustrate sketching the voltage and current at the terminations
as a function of time, Example 4.2.
 4.3 THE TIME-DOMAIN SOLUTION 213

FIGURE 4.17 Example 4.3. Illustration of the effect of pulsewidth on the terminal voltages:
(a) the problem specification; (b) the voltage at the input to the line; (c) the load voltage.
214 TRANSMISSION LINES AND SIGNAL INTEGRITY

and the load reflection coefficient is

1  100
GL ¼
1 þ 100
¼1

The one-way time delay is

L
TD ¼
v
¼ 1 ns

First we sketch the source voltage, V(0, t). The initially sent out voltage is

100
 20 ¼ 5 V
300 þ 100

The incident and reflected voltages are again sketched in Fig. 4.17b with dashed
lines with an arrow added to indicate whether they are associated with a forward-tra-
veling or a backward-traveling wave. The incident pulse is sent to the load, arriving
there after one time delay of 1 ns, where it is reflected as a pulse of 5 V because the
load reflection coefficient is GL ¼ 1. This pulse reflected at the load arrives at the
source after an additional 1-ns time delay. This incoming pulse is reflected as
GS  5 V ¼ 2:5 V, which arrives at the load after 1 ns, where it is reflected as
2.5 V, arriving at the source after a 1-ns delay. The process continues as shown.
Adding all the incident and reflected pulses at the source, we obtain the total
voltage drawn with a solid line. Clearly, this total decays to zero, as it should in
steady state.
Now we sketch the voltage at the load. After a time delay of 1 ns, the initially sent
out voltage of 5 V arrives at the load and a reflected voltage of 5 V is sent back
toward the source. This reflected voltage arrives at the source after 2 ns, and a
reflected voltage of 2.5 V is sent back toward the load and arrives there at 3 ns.
When this pulse reflected at the source arrives at the load, a reflected voltage of
2.5 V is sent back toward the source, which is reflected at the source as 1.25 V, arriv-
ing at the load at 5 ns. These incident and reflected voltages are sketched in
Fig. 4.17c. Adding the voltages present at any one time gives the total as shown
by a solid line. Clearly this load voltage is decaying to zero, as it should in steady
state.

Example 4.4 This example illustrates the effect of a pulsewidth that is greater than
the round-trip delay. Consider the coaxial cable shown in Fig. 4.18a. The source
voltage is a pulse of 100 V amplitude and 6 ms duration. The line is specified by
its per-unit-length capacitance and inductance: c ¼ 100 pF=m and l ¼ 0:25 mH=m.
This corresponds to the RG58U coaxial cable whose per-unit-length parameters
were computed in Review Exercise Problem 4.3. The line has a characteristic
 4.3 THE TIME-DOMAIN SOLUTION 215

FIGURE 4.18 Example 4.4. Illustration of the effect of pulsewidth on the terminal voltages:
(a) the problem specification; (b) the voltage at the input to the line.
216 TRANSMISSION LINES AND SIGNAL INTEGRITY

impedance of
rffiffiffi
l
ZC ¼
c
¼ 50 V

The velocity of propagation is

1
v ¼ pffiffiffiffi
lc
¼ 200 m=ms

The source resistance is 150 V (RS ¼ 150 V), and the load resistance is a short
circuit (RL ¼ 0 V). Sketch the voltage at the input to the line.

Solution: The source reflection coefficient is

150  50
GS ¼
150 þ 50
1
¼
2
and the load reflection coefficient is
0  50
GL ¼
0 þ 50
¼ 1

The one-way time delay is

L
TD ¼
v
¼ 2 ms

The initially sent out voltage is

50
 100 ¼ 25 V
150 þ 50
The incident and reflected voltages are again sketched with dashed lines in Fig. 4.18b
with an arrow added to indicate whether they are associated with a forward-traveling
or a backward-traveling wave. The incident pulse is sent to the load, arriving there
after one time delay of 2 ms, where it is reflected as a pulse of 225 V. This pulse
reflected at the load arrives at the source after an additional 2-ms time delay. This
incoming pulse is reflected as 212.5 V, which arrives at the load after 2 ms,
 4.3 THE TIME-DOMAIN SOLUTION 217

where it is reflected as 12.5 V, arriving at the source after a 2-ms delay. The process
continues as shown. Adding all the incident and reflected pulses at the source, we
obtain the total voltage drawn with a solid line. Clearly this total decays to zero,
as it should in steady state.
Observe that in this example the pulsewidth of 6 ms is three time delays. Hence
the initially sent out pulse and the arriving pulse (which was the sent out pulse
reflected at the load) overlap. This overlap creates a rather interesting and compli-
cated waveform.

This graphical process is conveniently shown by the “bounce” or lattice diagram

in Fig. 4.19. From this we can write an expression for the voltage at z ¼ 0 and at the
load, z ¼ L, as

ZC
V(0, t) ¼ ½VS (t) þ (1 þ GS )GL VS (t  2TD )
RS þ ZC
þ (1 þ GS )(GS GL )GL VS (t  4TD )
þ (1 þ GS )(GS GL )2 GL VS (t  6TD ) þ    (4:53a)

and

ZC
V(L, t) ¼ ½(1 þ GL )VS (t  TD ) þ (1 þ GL )GS GL VS (t  3TD )
RS þ ZC
þ (1 þ GL )(GS GL )2 VS (t  5TD )
þ (1 þ GL )(GS GL )3 VS (t  7TD ) þ    (4:53b)

So the total voltages are the sum of the source voltage waveforms scaled and delayed
by multiples of the one-way time delay, TD . Although the source and load voltage
waveforms could be sketched from (4.53), it is much simpler to “trace the individual
incident and reflected waves” and at any time add all those present at that time as
was done graphically in the preceding examples. Observe that if the line is
matched at the load, RL ¼ ZC , then the load reflection coefficient is zero, GL ¼ 0,
and (4.53) reduce to

ZC
V(0, t) ¼ VS (t) R L ¼ ZC (4:53c)
R S þ ZC
ZC
V(L, t) ¼ VS (t  TD ) RL ¼ ZC (4:53d)
R S þ ZC

In this case the only effect of the line is to impose a time delay. The input and output
voltages of the line are identical; the line “doesn’t matter.”
218 TRANSMISSION LINES AND SIGNAL INTEGRITY

FIGURE 4.19 The “bounce diagram” for determining the voltages on the line at different
instants of time.

4.3.2 The SPICE Model

The previous section has demonstrated a graphical method of sketching the time-
domain solution of the transmission-line equations. It is frequently desirable to
have a numerical method that is suitable for a digital computer and will handle non-
linear as well as dynamic loads. The following method is attributed to Branin, and
was originally described in [10]. It is valid only for lossless lines. The method is
implemented in the SPICE (or PSPICE) circuit analysis program. For a thorough
review of the SPICE program, its various models, and rules for writing a
program, see [11] and Appendix D.
 4.3 THE TIME-DOMAIN SOLUTION 219

In order to obtain the required equations, we simply manipulate the solutions of

the lossless transmission-line equations given in (4.44). Rewrite these as
 z  z
V(z, t) ¼ V þ t  þ V t þ (4:54a)
v v
 z  z
ZC I(z, t) ¼ V þ t   V t þ (4:54b)
v v

Evaluating these at the source end, z ¼ 0, and the load end, z ¼ L, gives

V(0, t) ¼ V þ (t) þ V  (t) (4:55a)

ZC I(0, t) ¼ V þ (t)  V  (t) (4:55b)

and

V(L, t) ¼ V þ (t  TD ) þ V  (t þ TD ) (4:56a)
ZC I(L, t) ¼ V þ (t  TD )  V  (t þ TD ) (4:56b)

where the one-way time delay for the line is

L
TD ¼ (4:57)
v

Adding and subtracting (4.55) and (4.56) gives

V(0, t) þ ZC I(0, t) ¼ 2V þ (t) (4:58a)


V(0, t)  ZC I(0, t) ¼ 2V (t) (4:58b)
þ
V(L, t) þ ZC I(L, t) ¼ 2V (t  TD ) (4:58c)
V(L, t)  ZC I(L, t) ¼ 2V  (t þ TD ) (4:58d)

Shifting both (4.58a) and (4.58d) ahead in time by subtracting TD from t along with a
rearrangement of the equations gives

V(0, t) ¼ ZC I(0, t) þ 2V  (t) (4:59a)

V(L, t) ¼ ZC I(L, t) þ 2V þ (t  TD ) (4:59b)
V(0, t  TD ) þ ZC I(0, t  TD ) ¼ 2V þ (t  TD ) (4:59c)
V(L, t  TD )  ZC I(L, t  TD ) ¼ 2V  (t) (4:59d)

Substituting (4.59d) into (4.59a) gives

V(0, t) ¼ ZC I(0, t) þ E0 (L, t  TD ) (4:60a)

220 TRANSMISSION LINES AND SIGNAL INTEGRITY

where

E0 (L, t  TD ) ¼ V(L, t  TD )  ZC I(L, t  TD )

¼ 2V  (t) (4:60b)

Similarly, substituting (4.59c) into (4.59b) gives

V(L, t) ¼ ZC I(L, t) þ EL (0, t  TD ) (4:61a)

where

EL (0, t  TD ) ¼ V(0, t  TD ) þ ZC I(0, t  TD )

¼ 2V þ (t  TD ) (4:61b)

Equations (4.60) and (4.61) suggest the equivalent circuit of the total line shown in
Fig. 4.20. The controlled source EL (0, t  TD ) is produced by the voltage and
current at the input to the line at a time equal to a one-way transit delay earlier
than the present time. Similarly, the controlled source E0 (L, t  TD Þ is produced
by the voltage and current at the line output at a time equal to a one-way transit
delay earlier than the present time.

FIGURE 4.20 The SPICE (PSPICE) model of a transmission line: (a) an exact model of the
line; (b) the SPICE coding.
 4.3 THE TIME-DOMAIN SOLUTION 221

The equivalent circuit shown in Fig. 4.20 is an exact solution of the transmission-
line equations for a lossless, two-conductor, uniform transmission line. The circuit
analysis program SPICE (PSPICE) contains this exact model among its list of
available circuit element models that the user may call [11]. The model is the
TXXX element, where XXX is the model name chosen by the user. SPICE uses con-
trolled sources having time delay to construct the equivalent circuit of Fig. 4.20. The
user need only input the characteristic impedance of the line ZC (SPICE refers to this
parameter as Z 0) and the one-way transit delay TD (SPICE refers to this as TD).
Thus SPICE will produce exact solutions of the transmission-line equations. Fur-
thermore, nonlinear terminations such as diodes and BJTs, as well as dynamic ter-
minations such as capacitors and inductors, are easily handled with the SPICE code,
whereas a graphical solution or the hand solution of the equivalent circuit in
Fig. 4.20 for these types of loads would be quite difficult. This author highly rec-
ommends the use of SPICE for the incorporation of two-conductor transmission
line effects into any analysis of an electronic circuit. It is simple and straightforward
to incorporate the transmission-line effects in any time-domain analysis of an elec-
tronic circuit, and, more importantly, models of the complicated, but typical, non-
linear loads such as diodes and transistors as well as inductors and capacitors
already exist in the code and can be called on by the user rather than the user
needing to develop models for these loads.

Example 4.5 Use the SPICE (or the personal computer version, PSPICE) to solve
the problem shown in Fig. 4.16 that was obtained in Example 4.2.

Solution: The SPICE (PSPICE) coding is shown in Fig. 4.21a:

EXAMPLE 4.5
VS 1 0 PWL(0 0 .01U 30)
T 1 0 2 0 Z0=50 TD=2U
RL 2 0 100
.TRAN .01U 20U 0 .0lU
.PRINT TRAN V(2) I(VS)
*THE LOAD VOLTAGE IS V(2) AND
*THE INPUT CURRENT IS – I(VS)
.PROBE
.END

We have used the SPICE piecewise linear function (PWL) to specify the source
voltage. This function specifies a piecewise linear graph of it as a sequence of
straight lines between time points T1, T2, T3, . . . whose values are V1, V2,
V3, . . . as

VXXX N1 N2 PWL(T1 V1 T2 V2 T3 V3 . . .)
222 TRANSMISSION LINES AND SIGNAL INTEGRITY

FIGURE 4.21 Example 4.5; the SPICE solution of the problem of Example 4.2: (a) the
SPICE node labeling; (b) the SPICE solution for the line voltage; (c) the SPICE solution
for the input current to the line.
 4.3 THE TIME-DOMAIN SOLUTION 223

Also, we have specified the battery voltage with a very small (.01 ms) rise time in
order to specify it with the PWL function. We have used the .PROBE feature of
PSPICE to provide plots of the load voltage and input current which are shown in
Fig. 4.21b and Fig. 4.21c, respectively. Compare these to the corresponding plots
obtained manually and shown in Fig. 4.16
The format of the .TRAN line is

.TRAN [ print step] [ final solution time] [ print start]

[maximum solution time step]

The print step is the time interval that solutions are printed to a file if so requested in
a .PRINT statement, and the final solution time is the final time for which a solution
is desired. These first two parameters are required, and the remaining two are
optional. All solutions start at t ¼ 0 but the print start parameter delays the printing
of the results to an output file until this time. Usually the print start parameter is set
to zero. Specification of the remaining term, maximum solution time step, is often
required in order to control the accuracy and resolution of the solution. SPICE
(PSPICE) solves the equations of the transmission line and associated termination
circuits by discretizing the time interval into increments Dt. These are solved in a
“bootstrapping” fashion by updating the results at the next time step with those
from the previous intervals. The maximum solution time step parameter in
the .TRAN line sets that maximum discretization time step. When the circuit con-
tains a transmission line, the line voltages and currents will be changing in intervals
of time on the order of the one-way time delay TD as we have seen. In order to not
miss any such important variations, the maximum solution time step must be con-
siderably less than this one-way delay. The SPICE program developed in the
1960s automatically set the maximum discretization time step to be one-half of
the smallest line delay when the circuit contained transmission lines. In many pro-
blems the voltages and currents will be varying in time intervals much smaller than
this. For example, the source voltage waveform may be specified as having a rise/
falltime in order to specify it with the PWL function. This rise/falltime may be (and
usually is) much smaller than the line one-way delay. Hence the maximum solution
time step should be set on the order of the smallest time variation.

Example 4.6 Use the SPICE (or the personal computer version, PSPICE) to solve
the problem shown in Fig. 4.17 that was obtained in Example 4.3.

Solution: The SPICE (PSPICE) coding is shown in Fig. 4.22a:

EXAMPLE 4.6
VS 1 0 PWL(0 0 0.01N 20 1N 20 1.01N 0)
RS 1 2 300
T 2 0 3 0 Z0=100 TD=1N
RL 3 0 1E8
224 TRANSMISSION LINES AND SIGNAL INTEGRITY

FIGURE 4.22 Example 4.6; the SPICE solution of the problem of Example 4.3: (a) the
SPICE node labeling; (b) the SPICE solution for the input voltage to the line; (c) the
SPICE solution for the line load voltage.
 4.4 HIGH-SPEED DIGITAL INTERCONNECTS AND SIGNAL INTEGRITY 225

.TRAN 0.01N 10N 0 0.0lN

.PRINT TRAN V(2) V(3)
*THE LOAD VOLTAGE IS V(3) AND
*THE INPUT VOLTAGE IS V(2)
.PROBE
.END

We have again used the SPICE piecewise-linear function to specify the source
voltage. Also, we have specified the pulse with very small (0.01 ns) rise/falltimes
in order to specify it with the PWL function. The open-circuit load is specified as
a large (108 V) resistance. The input voltage and output voltage are shown in
Fig. 4.22b and Fig. 4.22c, respectively. Compare these to the corresponding plots
obtained manually and shown in Fig. 4.17.

Example 4.7 Use the SPICE (or the personal computer version, PSPICE) to solve
the problem shown in Fig. 4.18 that was obtained in Example 4.4.

Solution: The SPICE (PSPICE) coding is shown in Fig. 4.23a:

EXAMPLE 4.7
VS 1 0 PWL(0 0 .01U 100 6U 100 6.01U 0)
RS 1 2 150
T 2 0 3 0 Z0=50 TD=2U
RL 3 0 1E-6
.TRAN .01U 20U 0 .01U
.PRINT TRAN V(2) V(3)
*THE INPUT VOLTAGE IS V(2)
.PROBE
.END

Again we used the PWL function to specify the pulse. The short-circuit load is
represented with a 1-mV resistor since SPICE does not allow for zero-ohm resistors.
The input voltage to the line is shown in Fig. 4.23b. Compare this to the correspond-
ing plot obtained manually and shown in Fig. 4.18b.

4.4 HIGH-SPEED DIGITAL INTERCONNECTS AND SIGNAL INTEGRITY

Clock speeds in digital systems are increasing at a steady rate; PC clocks are on the
order of 3 GHz. Digital data transfer rates are similarly increasing. Both of these
signals are transferred from one point to another over the PCB lands. Of course,
the time delay in traversing the lands is becoming a critical factor in the overall
timing budget of the system with the time delays becoming on the order of the
pulse rise/falltimes. There are a number of problems associated with time delay,
one of which is clock skew. Suppose that a clock is fed to two modules as shown