library IEEE;

use IEEE.std_logic_1164.all;

entity fsm is
port(reset,E,clk : in std_logic;
Q : out std_logic_vector(1 downto 0);
z : out std_logic);
end fsm;

architecture fsm_arch of fsm is

type state_type is (S0,S1,S2,S3,S4);
signal PS, NS : state_type;
begin

sync_proc : process(clk,NS,reset)
begin
if(reset = '0') then
PS <= S1;
elsif (rising_edge(clk)) then
PS <= NS;
end if;
end process sync_proc;

comb_proc : process(PS,E)
begin
case PS is
when S1 =>
--z <= '0'; -- Moore
Q <= "00";
if(E = '0') then
NS <= S1;
z <= '0';
else
NS <= S2;
z <= '0';
end if;
when S2 =>
Q <= "01";
if(E = '0') then
NS <= S2;
z <= '0';
else
NS <= S3;
z <= '0';
end if;
when S3 =>
Q <= "10";
if(E = '0') then
NS <= S3;
z <= '0';
else
NS <= S4;
z <= '0';
end if;
when S4 =>
Q <= "11";
if(E = '0') then
NS <= S4;
z <= '1';
 else
NS <= S1;
z <= '1';
end if;
when others =>
NS <= S1;
z <= '0';
Q <= "00";
end case;
end process;
end fsm_arch;