CALIFORNIA STATE UNIVERSITY, BAKERSFIELD (CSUB)

DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING & COMPUTER SCIENCE

ECE 3220: DIGITAL DESIGN WITH VHDL

Homework 3
Solution

QUESTION 1 ( 30 POINTS):

Consider the function f (w1, w2, w3) = m(0, 2, 3, 4, 5, 7) and write VHDL code that represents this function using

one selected signal assignment.

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A NSWER

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY Q1 IS
PORT ( w : IN STD_LOGIC_VECTOR(1 TO 3) ;
f : OUT STD_LOGIC) ;
END Q1 ;

ARCHITECTURE Behavior OF Q1 IS
BEGIN
WITH w SELECT
f <= ‘0’ WHEN “001”,
‘0’ WHEN “110”,
‘1’ WHEN OTHERS;
END Behavior ;

1
QUESTION 2 (30 P OINTS ):
Actel Corporation manufactures an FPGA family called Act 1, which has the multiplexer based logic block
illustrated in the Figure. Show how the function f = w2w30 + w1w3 + w20 w3 can be implemented using only
one Act 1 logic block.

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A NSWER
f = w2w30 + w1w3 + w20 w3 = w3(w1 + w20 ) + w30 (w2) = w3(g ) + w30 (w2)
g = w1 + w20 = w2(w1) + w20 (1)
We may realize the function using the Actel building block as follows.

2
QUESTION 3 (40 P OINTS ):
Given the following Boolean functions
P = A ⊕ B ⊕C ⊕ D ⊕ E
Q = A ⊕ B ⊕C ⊕ F ⊕G
a) Decompose the functions in such a way that they can be produced with a network having only three 3-input
LUTS. (20 Points)
b) Draw the complete circuit specifying the truth table of each LUT. (20 Points)
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A NSWER
a) Let R = A ⊕ B ⊕C
Then, P = R ⊕ D ⊕ E and Q = R ⊕ F ⊕G, which suggest the following three 3-LUT circuit.