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Introduction To VIP With PCI Express Tec PDF
Introduction To VIP With PCI Express Tec PDF
Rutva Pathak1
M. E. Student[VLSI & Embedded systems Design]
1
Department of Electronics and Communication, Gujarat Technological University, Ahmedabad
I. INTRODUCTION
PCI Express (PCIe) is the third generation, general purpose
and high performance I/O bus used to interconnect
peripheral devices to a computer. PCI Express architecture
is a high performance, IO interconnect for peripherals in
computing/communication platforms Evolved from PCI
and PCI-X architectures Yet PCI Express architecture is
significantly different from its predecessors PCI and PCI-X
Fig. 2: Example topology
A. Root Complex:
Root Complex (RC) is the root of an I/O hierarchy and it
connects the CPU or memory subsystem to the I/O devices.
. It is shown in Fig 2 that a Root Complex may
Fig. 1: PCI Express Link support one or more PCI Express Ports. Each interface
Here the idea is to develop a Verification IP for PCI defines a separate hierarchy domain. Each hierarchy domain
Express. Verification IP are reusable verification modules may be composed of a single Endpoint or a sub-hierarchy
that typically consist of bus functional models, traffic containing one or more Switch components and Endpoints.
generators, protocol monitors, and functional coverage The capability to route peer-to-peer transactions
blocks. Each of the verification IP (VIP) accelerates the between hierarchy domains through a Root Complex is
development of a complete verification environment to cut optional and implementation dependent. For example, an
down the time to first test. implementation may incorporate a real or virtual Switch
Based on widely used and emerging protocols, internally within the Root Complex to enable full peer-to
verification IP are standards-compliant, plug and play peer support in a software transparent way.
modules that cut down overall verification time for B. Endpoints:
engineers using different HVL. They contain the necessary Endpoint is a type of Function that can be the Requester or
infrastructure for test-bench generation and checking Completer of a PCI Express transaction either itself or on
mechanisms, as well as all the appropriate routines to create behalf of a distinct non-PCI Express device (something
individual protocols or bus functional models. other than a PCI device or Host CPU), e.g., a PCI Express
Verification IP solutions enable verification attached graphics controller or a PCI Express-USB host
engineers to focus on verifying their designs rather than controller. Endpoints are classified as either legacy, PCI
spending an excessive amount of time setting up complex Express, or Root Complex Integrated Endpoints.
verification environments. Packets are transmitted and received serially and byte
striped across the available Lanes of the Link. The more
Lanes implemented on a Link the faster a packet is
transmitted and the greater the bandwidth of the Link.
2) A.2 TLP Packet Disassembly of Flow Control information. DLLPs are transferred
A neighboring receiver device receives the incoming TLP between Data Link Layers of the two directly connected
bit stream. As shown in Fig 6 the received TLP is decoded components on a Link. DLLPs do not pass through switches
by the Physical Layer and the Start and End frame fields are unlike TLPs which do travel through the PCI Express fabric.
stripped. DLLPs do not contain routing information. These packets
The resultant TLP is sent to the Data Link Layer. are smaller in size compared to TLPs, 8 bytes to be precise.
This layer checks for any errors in the TLP and strips the 1) DLLP Assembly
sequence ID and LCRC field. Assume there are no LCRC The DLLP shown in Fig 8 on page 76 originates at the Data
errors, then the TLP is forwarded up to the Transaction Link Layer. There are various types of DLLPs some of
Layer. If the receiving device is a switch, then the packet is which include Flow Control DLLPs (FCx), acknowledge/ no
routed from one port of the switch to an egress port based on acknowledge DLLPs which confirm reception of TLPs
address information contained in the header portion of the (ACK and NAK), and power management DLLPs (PMx). A
TLP. DLLP type field identifies various types of DLLPs. The
Data Link Layer appends a 16-bit CRC used by the receiver
of the DLLP to check for CRC errors in the DLLP.
IV. VERIFICATION
A. Importance of VIP:
Advanced verification techniques allow the user to increase
the quality and level of verification. New test bench
languages support more sophisticated types of testing, such
as advanced random testing methods. Coverage tools enable
the users to determine the how much verification is done on
Fig. 8: DLLP Origin and Destination different parts of the code providing some feedback on the
quality.
V. CONCLUSION
PCI Express is a high speed serial protocol which is more
suitable for high speed applications than other bus protocols
like PCI and PCI-X. Verification is one of the most
important tasks for any ASIC design. It is very tough task to
verify a complex protocol like PCIe. There comes need of
VIP. A VIP is a reusable, configurable and easy to deal
verification component user can verify many scenarios and
condition with this and as it is reusable component, one
may do changes for different generations or versions as per
requirement and do the verification with randomization.