Experiment No: 2 Date:

Design & Implementation of Half Adder using logic gates

Objective:
To study behaviour of Half Adder using logic gates.

Components Required:

Sl .No Description Range Quantity

1 Digital IC Trainer kit 1
2 IC 7432 ( OR) 1
3 IC 7408 ( AND) 1
4 IC 7404 ( NOT) 1
5 IC 7486 ( EX-OR) 1
6 Connecting wires As required

HALF ADDER:
A half adder has two inputs for the two bits to be added and two outputs one from the
sum ‘ S’ and other from the carry ‘ c’ into the higher adder position. Above circuit is called as a
carry signal from the addition of the less significant bits sum from the X-OR Gate the carry out
from the AND gate.

Procedure:
1) Connections are given as per the circuit diagram.
2) Inputs are given to the circuit making high ‘1’ to +Vcc supply to the 14th pin and for low
‘0’ is ground to the 7th pin of the gate.
3) Depending upon the truth table, if the LED glows it represents ‘1’ and if it does not glow,
it represents ‘0’.
4) Verify the truth table as given.

LOGIC DIAGRAM:

HALF ADDER
TRUTH TABLE:

A B CARRY SUM

0 0
0 1
1 0
1 1

K-Map for SUM: K-Map for CARRY:

Boolean Expressions :

Result:

Discussion:

Conclusion:

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