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as expected. Fig. 3 Using SR flip flop and gates layout design of 4 bit synchronous up counter in cadence using
180nm technology As shown in the figure above is the layout design of the four bit synchronous up counter which is
designed by integrating the layout of the single four bit synchronous counter. IV. RESULT AND SIMULATION: The 4
bit synchronous up counter is designed using the 180nm technology in the cadence virtuoso and it’s layout is
further made from it and the figure 3 given above can be considered as the layout. Now the floor plan of the
counter designed is being done in the 180nm technology of cadence.the figure 4 shown below is the floor plan of
the 4bit synchronous up counter using 180nm technology of cadence. Fig.4Floor planning of 4 bit synchronous up
counter in cadence In order to maintain the privacy of patients information of not disclosing it to others this floor
map is designed so that the data of one patient should in one to one correspondence with the counters aligned in
the queue and should be at the distance away from the staff patient communication so hence the privacy of a
patient is maintained and is not disclosed to others. In order to reduce the glitch violations I the circuit the circuit or
the layout is simulated number of times and through each iteration simulation report is created ,from the report
through which the glitch violations become zero is considered as the final floor map and the layout . As the report of
the first two iterations is not satisfactory we have done the simulation three times in order to get the best possible
synthesis report and the least glitch violations. So in the iteration 3 we get the desired output and the no of
iterations in total are three. So, we have design the desired 4 bit synchronous up counter using 180 nm technology
of cadence and its floor planning is done in a way so that a patient’s privacy is maintained in the health care system
and the hospitals. V. CONCLUSION The floor planning for the 4 bit synchronous up counter is done using the 180 nm
technology and the corresponding output is recorded . from the our observations we can conclude that a counter
will be in it’s most efficient stage if it has the least area consumed and the least power consumption. This is
achieved in the initial circuit design of the cadence. In this method of the counter design all these characteristics
are achieved. by doing so, in floor planning the number of glitch violations are reduced and hence the patient’ s
information privacy is maintained. Future work in this field of floor planning of counters for health care applications
can be proceeded using the parallel circuitry. REFERENCES [1] Yogita Hiremath1, Akalpita L. Kulkarni2, J. S.
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