Real Time

Technical Clock
Data Sheet(RTC)

Technical Data Sheet

Part Number: T-CS-PE-0003-100

Document Number: I-IPA01-0026-USR Rev 10

February 2007

i
Real Time Clock (RTC)
©2003 Cadence Design Systems Inc. All rights reserved

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 RTC Technical Data Sheet

Real Time Clock (RTC)

Features
• Uses the AMBA APB protocol, version 2.0
• Complete time of day clock: 12/24 hour, hours, minutes, seconds and hundredths
• Calendar function: day of week, date of month, month, year, century, leap year
compensation, and year 2000 compliant.
• Alarm function: month, date, hour, minute, second and hundredths resolution
• Event function: can set interrupt for every roll over of month, day, hour, minute,
second or hundredth-second
• Speed of Operation: APB clock domain 100 MHz in a typical 0.25 µm technology;
counter clock speed of 100 Hz or 1 Hz (compile option)
• Power down mode with standby_pclk clock option
• Optional byte addressing mode for APB
• Time and calendar registers available as core outputs with associated changed
indicator.

Description
The Real Time Clock (RTC) module keeps track of time of day, to an accuracy of one
hundredth of a second (with 100 Hz clock - one second with 1 Hz clock), and has calendar
functionality keeping track of the day, month and year. The RTC comprises of a binary coded
decimal counter with the following data:
• Year from 1900 to 2999
• Month from 1 to 12
• Date from 1 to 28, 29, 30 or 31 (as a function of month and year)
• Day of week from 1 to 7 (mapping to date is not fixed)
• Hour from 0 to 23, or from 1 to 12 with the AM/PM flag set
• Minute from 0 to 59
• Second from 0.00 to 59.99 (or 0 to 59 with 1Hz clock)
An alarm register allows comparison of month, date, hour, minute, second and
hundredth-second. Each of these may be masked (that is forced to equality), so that, for
example, an alarm can be generated at 12:37 on the 15th of every month. An interrupt can be
generated on an alarm event.
Event detection is also available. This will generate an interrupt every time the time or
calendar register rolls over into a new month, date, hour, minute, second or
hundredth-second.

Signal Interfaces
The RTC module has the following signal interfaces:
• RTC control, clock and interrupt signals
• AMBA Advanced Peripheral Bus (APB) slave interface (32-bit and 8-bit
configurations available)
• Power on, APB and RTC reset signals
• Time and calendar register outputs
The APB interface fully conforms to the ARM AMBA Revision 2.0 specification.

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 RTC Technical Data Sheet

RTC Control and Interrupt Signals

clk_cnt rtc_int
rtc_changed
standby_pclk Real Time Clock
time_o
calendar_o

AMBA APB

RTC Signals
Signal Name I/O Description
clk_cnt I 100 Hz or 1Hz clock for counter (compile option)
standby_pclk I Standby clock for power-down operation
rtc_int O Interrupt from Real Time Clock.
time_o O Time value
31: reserved
30: Indicates PM in 12-hour mode
29:24: Hours (2-digit BCD)
23:16: Minutes (2-digit BCD)
15:08: Seconds (2-digit BCD)
07:00: Hundredths of seconds (2-digit BCD)
calendar_o O Calendar value
31:16: Year (4-digit BCD)
15:08: Day (of month – 2-digit BCD)
07:03: Month (2-digit BCD)
02:00: Day (of week – mapping is programmable)
rtc_changed O Time and calendar register have changed (either by counting
or set)

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 RTC Technical Data Sheet

Reading and Interrupt Timing from RTC

Tclk Two cycles setting period before new value available

standby_pclk

penable

psel

paddr

pwrite

prdata

clk_cnt

counter TIME = T TIME = T+1

time
TIME = T TIME = T+1
calendar
Tohint
rtc_int
Tovint N2 cycles
rtc_changed N1 cycles

Note: The number of cycles between time and counter outputs changing and the
assertion of rtc_changed (N1) and the number of cycles for which rtc_changed
is asserted (N2) are compile-time parameters.
Parameter Description Min Max Unit
Tclk Clock period, T0 5 See ns
Note
Tohint Interrupt, time, calendar hold after pclk 0.1 - ns
Tovint Interrupt, time, calendar valid after pclk - 30% × T0

Note: The maximum period for standby_pclk is such that there must be >2+N1+N2
cycles of standby_pclk for each cycle of clk_cnt.

AMBA APB Slave Interface

pclk
n_p_reset
psel
AMBA APB
penable Slave prdata
Interface
pwrite
paddr
pwdata

Signal Name I/O Function

pclk I APB clock
n_p_reset I APB reset (active low, asynchronous with pclk)
psel I APB select
penable I APB enable
pwrite I APB read/write strobe

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 RTC Technical Data Sheet

paddr I APB address bus (only LSBs used, [5:0])

pwdata I APB write data
prdata O APB read data

APB Timing Characteristics

The following characteristics have been set as the default values for the synthesis of the
module:
Tclk
pclk
Tihpen
Tispen
penable
Tispsel Tihpsel
psel
Tispa Tihpa
paddr
Tispw Tihpw
pwrite
Tispwd Tihpwd
pwdata
Tohprd
prdata
Tovprd

Parameter Description Min Max Unit

Tclk Clock period, T0 10 Note 2 ns
Tihpen penable hold after pclk 0.1 - ns
Tispen penable setup before pclk 50% - T0
Tihpsel psel hold after pclk 0.1 - ns
Tispsel psel setup before pclk 50% - T0
Tihpa paddr hold after pclk 0.1 - ns
Tispa paddr setup before pclk 50% - T0
Tihpw pwrite hold after pclk 0.1 - ns
Tispw pwritw setup before pclk 50% - T0
Tihpwd pwdata hold after pclk 0.1 - ns
Tispwd pwdata setup before pclk 50% - T0
Tohprd prdata hold after pclk 0.1 - ns
Tovprd prdata valid after pclk - 30% T0

Note 1: All timings are specified relative to the target clock period, T0. These are coded
into the synthesis script provided. These timings have been achieved with a
typical 0.13 µm technology, but are for guidance only.

Note 2: pclk must be either synchronous to standby_pclk and of the same frequency
and phase, or it may be stopped.

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 RTC Technical Data Sheet

Reset Signals

n_rtc_reset

n_p_reset n_rtc_reset_out
RTC
n_pon_reset

Signal Name I/O Function

n_pon_reset I Power on reset. Resets the keep_RTC and control
registers.
n_p_reset I APB reset (active low, asynchronous with pclk).
Re-initialzses all interrupt registers, alarm registers, status
registers and alarm enable register.
n_rtc_reset I RTC reset. Re-initializes 12/24 hour, time, calendar and
events.
n_rtc_reset_o O See following notes.
ut

Note 1: n_rtc_reset_out is low when either n_pon_reset is low or when

n_p_reset and the value of keep RTC register is low.

Note 2: Clock tree insertion can be performed on the reset line when n_rtc_reset_out
is connected to n_rtc_reset.

Programming Interface
Each register address is defined by an offset in paddr[7:0] as in the table below. External
circuitry is required to generate psel as the required decode of paddr[31:8].

Register Map
Offset Name Access Description
0x0000 Control RW Start and stop timing and calendar
0x0004 12/24 hour RW Set 12/24 hour mode
0x0008 Time RW Contains time values and data valid flag
0x0008~
0x000B
0x000C Calendar RW Contains date values and data valid flag
0x000C
~0x000F
0x0010 Time alarm RW Contains time values for alarm
0x0010~
0x0013
0x0014 Calendar RW Contains date values for alarm
0x0014~ alarm
0x0017

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 RTC Technical Data Sheet

0x0018 Alarm enable RW Enables alarming on: month, date, hour,

minute, second and hundredths
0x001C Event flags RW Flags for alarm and roll-over events. Note that
there is write access for verification purposes
only and should not be written to in sytem
usage.
0x0020 Interrupt WO Enables alarm and roll-over events
enable
0x0024 Interrupt WO Disables alarm and roll-over events
disable
0x0028 Interrupt RW Masks off alarm and roll-over events
mask
0x002C Status RW Valid data flags
0x0030 Keep RTC RW Controls functionality of n_rtc_reset_out
signal
Note 1: The interrupt enable and disable registers are not real registers and so may not be
read from.

Note 2: When the 1 Hz clock input option is compiled, the hundredth of a second fields are
reserved. This applies to all registers with hundredths fields.

Note 3: In byte-addressing mode, registers with more than 8 actively used bits are
allocated several addresses. paddr[1:0] is used to address the byte within the
register.

Physical Estimates
The figures below have been achieved in synthesis to a standard 0.13 µm technology.
Gate count 4000 2i/p NAND equivalents
FF count 120~135 FFs clocked by pclk
109~119 FFs clocked by standby_pclk
Power 27 µW at 200 MHz in standby-mode
770 nW at 32 kHz in standby-mode
SOC-Internal pins (in) 50
SOC-Internal pins (out) 36
SOC-External pins (in) 1
SOC-External pins (out) None

Verification
All our IP modules are verified to one of the following levels.
• Gold IP has been to target silicon.
• Silver IP has been to silicon in FPGA.
• Bronze IP has been verified in simulation with logical timing closure.
• In development IP has not yet been verified.
Please contact the IPGallery™ (ipgallery@cadence.com) for the latest verification
information.

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 RTC Technical Data Sheet

Deliverables
The full IP package comes complete with:
• Verilog HDL
• Cadence RTL Compiler synthesis scripts with SDC constraints
• Verilog testbench
• RTC User’s Guide with full programming interface, parameterization instructions and
synthesis instructions.

Document No: I-IPA01-0026-USR Rev 10, February 2007

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