Jon Sandström (jon_sandstrom@asus.

com)
2018-04-19

ENTHUSIAST HIGHLIGHTS
ROG CROSSHAIR VII HERO
Version 0.3 (BIOS 0509)

1. Voltage regulation

Since the Crosshair VII Hero doesn’t have display outputs, the CPU Core and SOC phase
configuration has been changed to 10+2 (on C6H it’s 8+4). The power stages are also upgraded
to Infineon IR3555 rated at 60A.

The phases have been re-arranged for better thermal balance, where the seldom stressed SOC
phases are placed between the CPU Core phases to reduce temperatures. The VRM temperature
readings on C7H rely on reporting form the power blocks, while C6H relied on an external
thermistor. The controller readings are therefore not directly comparable. This can be easily
verified by thermal imaging or external temperature measurements.

1.1. Thermal imaging

Thermal imaging tests were conducted with a Ryzen 7 2700X at 4.0 GHz with CPU Core
Voltage at 1.43 V. No other settings than CPU Core Ratio and CPU Core Voltage were changed
in BIOS. The system was then stressed with Prime95 29.1 Small FFTs 12k for at least 30
minutes. CPU output power was 175W on both systems. All temperatures are measured in
degrees Celsius. Note that both boards are tested without heatsinks.

CPU Tctl reading = 92*C

C6H VRM controller reading = 92*C

C7H VRM controller reading = 80*C

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1.1.1. Crosshair VI Hero

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1.1.2. Crosshair VII Hero

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2. Asynchronous eCLK mode

C7H supports two different modes for external reference clock adjustments, Synchronous and
Asynchronous (Pinnacle Ridge only).

Synchronous mode works just like before, affecting all parts of the CPU except on-chip IO like
USB. Core/DRAM/PCIE/FCLK are all based on the same reference clock.

Asynchronous mode is new and allows the CPU Core to use one reference clock, while
DRAM/PCIE/FCLK uses another. This allows overclocking the CPU Core using reference clock
adjustments without affecting DRAM/PCIE/FCLK frequencies. The main advantage is being
able to keep PCI-E devices at default, as some don’t work well with increased frequencies.
BCLK 1 Frequency adjusts DRAM/PCIE/FCLK and BCLK 2 Frequency adjusts the CPU Core.

There’s currently one disadvantage, with a slight read/copy memory reduction (2-300 MB/s) and
a larger latency penalty (~15-20 ns) when using the Asynchronous mode. At the time of writing
there’s no fix for this, and it’s not certain there will be one.

AIDA64 v5.95 Memory Benchmark Read Write Copy Latency

3.8G 3200CL16 Synchronous 48607 MB/s 47266 MB/s 44787 MB/s 68,3 ns
3.8G 3200CL16 Asynchronous 48339 MB/s 47245 MB/s 44473 MB/s 87,2 ns

When testing reference clocking, make sure to use any of the four bottom SATA ports. The
X470 chipset has an issue with the two top SATA ports when adjusting PCI-E frequency. This
usually manifests in getting stuck at A2 Q-Code during POST.

There are also a few timer related issues when adjusting the reference clock in real-time (in the
operating system). The current recommendation is to only adjust it from BIOS, and make sure to
use CPU-Z v1.84 or newer.

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3. Performance Enhancer

With eXtended Frequency Range (XFR) version 2, there are configurable options which can
increase boost frequencies and duration. The available options are PPT, TDC and EDC under
“Advanced\AMD CBS\NBIO Common Options\Precision Boost Override Configuration”. The
BIOS item “Performance Enhancer“ tunes these options in a simple way. Level 1 and 2 rely only
on the AMD provided options mentioned. Level 3 and 4 has a few tweaks of our own (with the
help from The Stilt) which causes XFR to always boost to the highest possible frequency. When
using Level 3/4, make sure to use the Balanced power profile, or adjust the “Minimum Processor
State” to below 50% on your preferred profile. Otherwise, Core Performance Boost (CPB) will
not work properly and single threaded performance will suffer. Additionally there’s a grace
period of roughly a minute after entering the operating system until P-states are engaged properly.

Each CPU is different and boosts to different frequencies, the same settings on two different
samples will give different results. The increased frequencies might be too high for some CPUs
or require additional voltage. When using this function, it’s best to rely on Offset Mode for the
CPU Core Voltage.

3.1. Overclocking with Performance Enhancer

A major tradeoff when overclocking on Ryzen CPUs has been that single-threaded performance
is suboptimal, as CPB is disabled as soon as the CPU Core Ratio is increased above default (OC
Mode). Typically, the maximum overclocked multi-threaded frequency is lower or at best
matching the default single-threaded frequency. Since it’s now possible to avoid power
limitations imposed on XFR, overclocking through the reference clock can be very rewarding.

The below test was done with a Ryzen 7 2700X and an AIO 240mm cooler.

Cinebench R15 1T Cinebench R15 nT

Configuration Score Frequency Score Frequency
Default 176 cb 4341 MHz 1798 cb 4017 MHz
PE = Level 3 176 cb 4341 MHz 1837 cb 4117 MHz
PE = Level 3 + 103.4 MHz Refclk 188 cb 4498 MHz 1936 cb 4265 MHz

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BIOS settings used (under Extreme Tweaker):

• Ai Overclock Tuner = Manual

o eCLK Mode = Synchronous mode
o BCLK Frequency = 103.4
• Performance Enhancer = Level 3 (OC)
• CPU Core Ratio = 37.00 (on 2700X, default for the used CPU)
• Memory Frequency = DDR4-3308 MHz (3200 MHz ratio)
• Core Performance Boost = Enabled
• CPU Core Voltage = Offset mode
o CPU Offset Mode Sign = +
o CPU Core Voltage Offset = 0.05000

4. Improved voltage monitoring

The ProbeIt measurement points are changed from surface pads, to plated hole-through points.
The multimeter probe tips fixes into them and prevents accidental scratching of the PCB. Both
ProbeIt points and software voltage reporting has higher accuracy, especially during load
conditions. This has been achieved by using a combination of differential sensing, on-die sense
points available on the CPU, as well as relying on the VRM controllers high-accuracy ADC
instead of the Super IO chip. Readings from the SIO are also enhanced, where the resolution is
decreased from 21.8mV to 10.9mV. Some of the improved readings are currently only available
in BIOS and AiSuite. Third party software support will be added soon.

The SIO 12V reading is also differential and sourced from the EATX12V connector making it
possible to compare 12V voltage droop between PSUs and connector configurations.

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Voltage item ProbeIt BIOS/AiSuite reading 3rd party software
CPU Core Voltage Differential Differential from Differential from SIO
ASP1405 (1mV) (10.9mV)
CPU SOC Voltage Differential Differential from Differential from SIO
ASP1405 (1mV) (10.9mV)
DRAM Voltage Differential Differential from Differential from SIO
ASP1103 (10mV) (10.9mV)
1.8V PLL Voltage Single-ended Single-ended from SIO Single-ended from SIO
(21.8mV) (21.8mV)
1.05V SB Voltage Single-ended Single-ended from SIO Single-ended from SIO
(10.9mV) (10.9mV)
12V N/A Differential from SIO Differential from SIO
(54.5mV) (54.5mV)
5V N/A Single-ended from SIO Single-ended from SIO
(27.25mV) (27.25mV)
3.3V N/A Single-ended from SIO Single-ended from SIO
(21.8mV) (21.8mV)

5. Memory overclocking
DIMMs per channel DIMM Rank Typical configuration Minimum Maximum
1 DPC Single 2x8GB 3466 MHz 3733 MHz
1 DPC Dual 2x16GB 3333 MHz 3466 MHz
2 DPC Single 4x8GB 3066 MHz 3333 MHz
2 DPC Dual 4x16GB 3066 MHz 3200 MHz

The specific CPU sample memory controller seems to have a larger influence on Pinnacle Ridge
compared to Summit Ridge. Numbers are with Samsung B-die based memory and fully stable
passing any memory test.

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6. Stealth mode

On-board indicator LEDs and Aura LEDs are now fully controllable by the user, allowing
complete control of which LEDs are enabled both during standby and runtime. For example, the
Q-Code display can be disabled after POST along with the on-board Power button and HDD
LEDs to make sure nothing interferes with the Aura scheme. Or you can disable Aura completely
and only keep the indicator LEDs enabled when needed the most.

7. I/O configuration

There are a few changes to I/O configuration on C7H compared to C6H. Most noticeable is the
addition of a second M.2 slot. The number of SATA ports is reduced from 8 to 6, which enables
the PCIEX4_3 slot to continue operating at x4 bandwidth even after plugging cards in the
PCIEX1_1 and PCIEX1_2 slots.

7.1. PCI-Express

Connector Bandwidth Source Note

PCIEX16/X8_1 x16/x8 Gen3 CPU x8 if M.2_2 is used
PCIEX1_1 x1 Gen2 X470
PCIEX8_2 x8/x4 Gen3 CPU x4 if M.2_2 is used
PCIEX1_2 x1 Gen2 X470
PCIEX4_3 x4 Gen2 X470
M.2_1 x4 Gen3 CPU
M.2_2 x4 Gen3 CPU Shared with PCIEX16/X8_1 and PCIEX8_2

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7.2. USB

Connectors Speed Source Note

Back PS/2 combo 2x Type-A (black) USB2.0 X470 Bottom port for USB BIOS Flashback
Back Top 4x Type-A (blue) USB3.0 CPU
Back Bottom 4x Type-A (blue) USB3.0 X470
Back 1x Type-A + 1x Type-C (red) USB3.1 ASM3142
Front USB1112 USB2.0 X470
Front ROG_EXT USB2.0 X470 Only the bottom pins are routed
Front U31G1_910 USB3.0 X470
Front U31G2_E1 USB3.1 X470

7.3. SATA

Connector Bandwidth Source Note

SATA6G_12 6 Gb/s X470
SATA6G_34 6 Gb/s X470
SATA6G_56 6 Gb/s X470 Don't use if adjusting PCI-E Frequency