Agenda: Day Two 6-1

DAY Unit I/O Paths and Exceptions Lab

2

5 Constraining I/O Interface Paths

6 Specifying Timing Exceptions

7 Introduction to Timing Models (QTM)

8 Performing STA

9 Summary

10 Customer Support
Specifying Timing Exceptions
Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

PrimeTime: Introduction to Static Timing Analysis 6-1 Unit 6: Specifying Timing Exceptions
 Unit Objectives 6-2

After completing this unit, you should be able to:

List 4 timing exception commands and state their

legal start and end points

Specify false path exception in 3 design examples

Write down the relationship between the Setup
and Hold Multipliers when applying a multicycle
path exception

State the command to look for ignored exceptions

Give 2 recommendations to specify timing
exceptions effectively

Specifying Timing Exceptions

Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

PrimeTime: Introduction to Static Timing Analysis 6-2 Unit 6: Specifying Timing Exceptions
 The Inputs and Outputs of PrimeTime 6-3

Gate-Level
Constraints Exceptions
Netlist

Technology
Setup
Libraries
File

Timing
SDF PrimeTime Models in
.db format

Log,
Reports Script
Files
Our Focus
Specifying Timing Exceptions
Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

PrimeTime: Introduction to Static Timing Analysis 6-3 Unit 6: Specifying Timing Exceptions
 Five Step Static Timing Analysis Flow 6-4

READ
READ

CONSTRAIN
CONSTRAIN

EXCEPTIONS
EXCEPTIONS

CHECK
CHECK

ANALYZE
ANALYZE
Our Focus
Specifying Timing Exceptions
Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

PrimeTime: Introduction to Static Timing Analysis 6-4 Unit 6: Specifying Timing Exceptions
 What are Timing Exceptions? 6-5

F1 F2

single clock cycle

Timing
Timingexceptions
exceptionsare
areused
usedto
tooverride
override
the
thedefault
defaultsingle-cycle
single-cycleconstraints
constraints
described
describedbybycreate_clock,
create_clock,
set_input_delay,and
set_input_delay, and
set_output_delay.
set_output_delay.

Specifying Timing Exceptions

Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

PrimeTime: Introduction to Static Timing Analysis 6-5 Unit 6: Specifying Timing Exceptions
 Timing Exception Commands 6-6

Timing
Timingexceptions
exceptionscan
canbe
beapplied
appliedto
toany
anytiming
timingpath:
path:

set_false_path Removes timing constraints from a timing path

set_multicycle_path Allows more than one clock cycle for a timing path

set_max_delay
Specifies max and min delays on paths
set_min_delay

report_exceptions Reports current timing exceptions

reset_path Restores the default timing constraints on

specified paths
Specifying Timing Exceptions
Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

PrimeTime: Introduction to Static Timing Analysis 6-6 Unit 6: Specifying Timing Exceptions
 Applying Exceptions 1/2 6-7

When using –from and –to options, you need to specify

legal path start and end points:
Start End Start & End

Input Ports and Output Ports

Clock Objects,
Clock Pins and Data Pins
Registers
of Registers of Registers

A D Q D Q

R1 R2
clk1
clk2

pt_shell> set_false_path –from A –to R1/D

pt_shell> set_false_path –from clk1 –to clk2

Specifying Timing Exceptions

Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

The complete commands for the example shown above should be:
set_false_path –from [get_pins A] –to [get_pins R1/D]
set_false_path –from [get_clocks clk1] –to [get_clocks clk2]

When specifying register cell names for the start and end points, (under the hood) PrimeTime will look
for the actual start and end pins of the register cell and apply the timing exception correctly for you.

You can be very specific with timing exceptions with -to/-from/-through options by specifying rise or
fall edges.
New options include:
-rise_from
-fall_from
-rise_to
-fall_to
-rise_through
-fall_through

PrimeTime: Introduction to Static Timing Analysis 6-7 Unit 6: Specifying Timing Exceptions
 Applying Exceptions 2/2 6-8

When using the –through option, any pin can be

used to describe the path:

D Q D Q
U12
Z
R1 R2

clk

pt_shell> set_false_path –through U12/Z

The path from R1/CP to R2/D will be false

Assumption: No fanin/fanout

Specifying Timing Exceptions

Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

When using the –through option, multiple –through arguments mean AND, multiple pins in one
–through are an OR.
Example:
set_false_path –through A –through B –through {C D}
means set a false path through the path that goes through “A and B and (C or D).”

PrimeTime: Introduction to Static Timing Analysis 6-8 Unit 6: Specifying Timing Exceptions
 Multiple Paths 6-9

pt_shell>
pt_shell> set_multicycle_path
set_multicycle_path 22 -from
-from FFA/CP
FFA/CP \\
-through
-through Multiply/Out
Multiply/Out -to
-to FFB/D
FFB/D

Two-Cycle Path -through

-from -to
In Multiply
Out
FFB
FFA
D

CP
sel
Add
One-Cycle Path

Specifying Timing Exceptions

Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

In this example, it is sufficient to specify Multiply/Out using the –through option, without the -from and
–to.

PrimeTime: Introduction to Static Timing Analysis 6-9 Unit 6: Specifying Timing Exceptions
 Logically False Paths 6-10

A
0 A
B 1 0
B 1
mux1
mux2

The paths through both A’s and both B’s cannot happen:

They are logical false paths!

Use the -through option:

set_false_path –through mux1/A –through mux2/A

set_false_path –through mux1/B –through mux2/B

Specifying Timing Exceptions

Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

You can find logical false paths with the “report_timing –true/-false/-justify”
command. This command will apply input combinations and trace through the netlist to find whether
the reported path is logically correct. Consult the PrimeTime User Guide for a detailed explanation.
Generally, you would only set this path as a false path if it appears in the timing reports with a violation.

PrimeTime: Introduction to Static Timing Analysis 6-10 Unit 6: Specifying Timing Exceptions
 Paths Between Asynchronous Clocks 6-11
FUNC_CORE
Des_A Des_B
CLKA
(100 Mhz N D Q D Q X D Q
from OSC1)

CLKB
(100 Mhz
from OSC2)

current_design FUNC_CORE

/* Make sure register-register paths meet timing */

create_clock -period 10 [get_ports CLKA]
create_clock -period 10 [get_ports CLKB]

/* Don’t optimize logic crossing clock domains */

set_false_path -from [get_clocks CLKA] -to [get_clocks CLKB]
set_false_path -from [get_clocks CLKB] -to [get_clocks CLKA]

Specifying Timing Exceptions

Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

CLKA and CLKB are asynchronous to each other.

To exclude Timing analysis between these 2 clock domains, specify the path(s) as false paths.

PrimeTime: Introduction to Static Timing Analysis 6-11 Unit 6: Specifying Timing Exceptions
 Constrain Tri-states at the Top-Level 6-12

Tri-states can be the cause of many false paths.

set_false_path -through [get_pins U1/DATA_BUS_OUT[1]] \
-through [get_pins U1/DATA_BUS_IN[1]]
U1 U2
UART TIMER

DATA_BUS_OUT DATA_BUS_IN

DATA_BUS
U3
CPU

TOP_BLOCK
Specifying Timing Exceptions
Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

PrimeTime: Introduction to Static Timing Analysis 6-12 Unit 6: Specifying Timing Exceptions
 Multi-cycle Paths 6-13

Clock
Clockperiod
periodis
is10
10ns.
ns.Per
PerSpecification,
Specification,the
the
adder
addertakes
takes66clock
clockcycles.
cycles.
How
Howdodoyou
youconstrain
constrainthe
thedesign?
design?

A D Q
64
A < 60 ns
E
C_reg

B D Q
+ D Q
64
Y

64
E
B
E

D Q
0 0 0 0 0 1
Clk
shift_reg

Specifying Timing Exceptions

Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

PrimeTime: Introduction to Static Timing Analysis 6-13 Unit 6: Specifying Timing Exceptions
 Timing with Multi-cycle Constraints 6-14

create_clock
create_clock -period
-period 10
10 [get_ports
[get_ports CLK]
CLK]
set_multicycle_path
set_multicycle_path 66 –setup
–setup -to
-to [get_pins
[get_pins C_reg[*]/D]
C_reg[*]/D]

Launch Capture

CLK
-10 0ns 10 20 30 40 50 60

C_reg/D IDEAL: TH < Adder_Delay < (60 - TSU)

C_reg/D

PT assumes change could occur near any clock edge causing metastability!

Where does PT perform hold analysis?

Specifying Timing Exceptions
Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

TSU = setup time

TH = hold time

PT will perform the setup analysis on edge 6, i.e. at 60 ns. This will allow the adder’s logic to have a
delay of (60 – setup_time – uncertainty).

PrimeTime: Introduction to Static Timing Analysis 6-14 Unit 6: Specifying Timing Exceptions
 Default Hold Check 6-15

set_multicycle_path
set_multicycle_path -setup
-setup 66 -to
-to [get_pins
[get_pins C_reg[*]/D]
C_reg[*]/D]
IMPLICIT! set_multicycle_path
set_multicycle_path -hold
-hold 00 -to
-to [get_pins
[get_pins C_reg[*]/D]
C_reg[*]/D]

Default
Hold
Check Capture
Launch

CLK
-10 0ns 10 20 30 40 50 60

C_reg/D (50 + TH) < Combo_Logic < (60 - TSU)

Why is hold check performed at 50 ns?

Specifying Timing Exceptions
Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

The default Hold check is always performed one edge before the setup check.
PT assumes that the clock edges at 10-50 ns can cause metastability if they occur at the same time the
data changes. Putting the hold check at 50 ns is the safest.

PrimeTime: Introduction to Static Timing Analysis 6-15 Unit 6: Specifying Timing Exceptions
 Set the Proper Hold Constraint 6-16

set_multicycle_path
set_multicycle_path -setup
-setup 66 -to
-to [get_pins
[get_pins C_reg[*]/D]
C_reg[*]/D]
OVERRIDE! set_multicycle_path
set_multicycle_path -hold
-hold 55 -to
-to [get_pins
[get_pins C_reg[*]/D]
C_reg[*]/D]

M H = MS - 1
Setup Check
Hold checks for : MH = 5 MH = 4 MH = 3 MH = 2 MH = 1 MH = 0
with MS = 6

CLK
-10 0ns 10 20 30 40 50 60

C_reg/D Now allows change between TH and (60 - TSU)

C_reg

D Q + D Q
E E
DESIRED RESULT: ALLOW 60ns for ADDER

Specifying Timing Exceptions

Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

MH stands for Hold Multiplier, MS for Setup Multiplier. The Setup multiplier counts up with
increasing clock cycles, the Hold multiplier counts up with decreasing cycles. The origin (0) for the
Hold Multiplier is always at the Setup Multiplier – 1 position.

PrimeTime: Introduction to Static Timing Analysis 6-16 Unit 6: Specifying Timing Exceptions
 Precedence of Timing Exceptions 6-17

F1 F2

More than one exception set

on the path from F1 to F2.
set_false_path has higher
precedence!
(see student notes)

clk1
clk2

set_false_path
set_false_path –from
–from clk1
clk1 –to
–to clk2
clk2
set_max_delay
set_max_delay 77 –from
–from F1
F1 –to
–to F2
F2
Specifying Timing Exceptions
Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

PrimeTime uses the following general precedence rules, when applying multiple exceptions to the same
path:
• set_false_path > set_max_delay or set_min_delay > set_multicycle_path
• pin > clock
• -from > -to > -through
• tighter constraint > looser constraint

For more detailed information refer to the PrimeTime User Guide: Advanced Timing Analysis.

PrimeTime: Introduction to Static Timing Analysis 6-17 Unit 6: Specifying Timing Exceptions
 Ignored Timing Exceptions 6-18

PrimeTime will warn you when invalid exceptions are applied.

pt_shell> set_false_path -from FF1/Q

Warning: Object 'FF1/Q' is not a valid
startpoint. (UITE-216)

How would you correct this exception?

Specifying Timing Exceptions

Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

set_false_path -from FF1/Q -- Invalid because this is an INVALID start point.

The exception needs the CLK pin of the flip-flop, so the correct syntax would be:
set_false_path -from FF1/CLK

PrimeTime: Introduction to Static Timing Analysis 6-18 Unit 6: Specifying Timing Exceptions
 Always Check for Invalid Exceptions 6-19

pt_shell> check_timing
Warning:
Warning: There
There are
are timing
timing exceptions
exceptions which
which are
are ignored.
ignored.

pt_shell> check_timing -verbose -ignored

Warning:
Warning: There
There are
are timing
timing exceptions
exceptions which
which are
are ignored.
ignored.
From
From To
To Setup
Setup Hold
Hold
---------------------------------------------------------
---------------------------------------------------------
FF1/Q
FF1/Q ** FALSE
FALSE FALSE
FALSE

Specifying Timing Exceptions

Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

To remove any unwanted exceptions, use the reset_path command, e.g.:

reset_path –from FF1/Q

You may also use the command report_exceptions –ignored to view ignored exceptions.

PrimeTime: Introduction to Static Timing Analysis 6-19 Unit 6: Specifying Timing Exceptions
 Reduce Number of Timing Exceptions 6-20

To reduce the run-time for timing analysis, minimize the total

number of exceptions!

The paths from F1_reg to F2_reg are false.

How many exceptions do each of the following commands generate?

32
F1 F2 F3

clk1
clk2
set_false_path
set_false_path -from
-from F1_reg[*]/CP
F1_reg[*]/CP -to
-to F2_reg[*]/D
F2_reg[*]/D 1

for
for {set
{set ii 1}
1} {$i
{$i <=
<= 32}
32} {incr
{incr i}
i} {{
set_false_path
set_false_path -from F1_reg[$i]/CP -to
-from F1_reg[$i]/CP -to F2_reg[$i]/D
F2_reg[$i]/D
2
}}

set_false_path
set_false_path -from
-from F1_reg[*]/CP
F1_reg[*]/CP 3
set_false_path
set_false_path -from
-from [get_clocks
[get_clocks clk1]
clk1] -to
-to [get_clocks
[get_clocks clk2]
clk2] 4
Specifying Timing Exceptions
Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

The most efficient way to specify timing exceptions is between clock domains!

PrimeTime: Introduction to Static Timing Analysis 6-20 Unit 6: Specifying Timing Exceptions
 Optimizing Analysis Time 1/2 6-21

The -through option requires more CPU for large designs

Do not use -through unless it is necessary

Sub-Optimal:
Sub-Optimal:
set_multicycle_path
set_multicycle_path 22 -from
-from U1/CP
U1/CP -through
-through U2/A
U2/A
-through
-through U3/B -through U4/A
U3/B -through U4/A
-through U5/C -to U6/D
-through U5/C -to U6/D

Optimal:
Optimal:
set_multicycle_path
set_multicycle_path 22 -to
-to U6/D
U6/D

To help PT’s run time, use -to option when possible.

Specifying Timing Exceptions

Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

PrimeTime: Introduction to Static Timing Analysis 6-21 Unit 6: Specifying Timing Exceptions
 Optimizing Analysis Time 2/2 6-22

Use set_disable_timing instead of set_false_path -through

when there is one pin.

Sub-Optimal:
Sub-Optimal:
ow

set_false_path
set_false_path -through
-through [get_pins
[get_pins ADDER/CI]
ADDER/CI]
Sl

Optimal:
Optimal:
st
Fa

set_disable_timing
set_disable_timing [get_pins
[get_pins ADDER/CI]
ADDER/CI]

Specifying Timing Exceptions

Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

PrimeTime: Introduction to Static Timing Analysis 6-22 Unit 6: Specifying Timing Exceptions
 Lab Overview and Review 6-23

LAB

Apply Multicycle and false path exceptions

on a complex design
60 min

Lab Review

 How do you know where in a design to apply

a multicycle path constraint?

 After applying a multicycle path constraint,

how can you verify the constraint has been
applied correctly?

Specifying Timing Exceptions

Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

Answers will follow.

PrimeTime: Introduction to Static Timing Analysis 6-23 Unit 6: Specifying Timing Exceptions
 Test For Understanding 6-24

A path between 2 flops are controlled by a 200 MHz clock.

The path delay is 13 ns worst case. Clock has a network
delay of 3 ns, and an uncertainty of 1 ns. Assume both
setup and hold time are 0.5 ns. The best case delay of
this path is known to be 6 ns. Write down the exceptions
such that there will not be any setup or hold violations:
______________________________________________
______________________________________________

 How can you constrain a path from an asynchronous

Reset input port to the Rst pin of a flop? The worst case
absolute delay is 3 ns and the best case absolute delay is
0.9 ns.
______________________________________________
______________________________________________

Specifying Timing Exceptions

Synopsys 34000-000-S16 PrimeTime: Introduction to Static Timing Analysis

PrimeTime: Introduction to Static Timing Analysis 6-24 Unit 6: Specifying Timing Exceptions