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    Digital System Design - UEC 612 Tutorial# 8

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    Lakshit Gupta
    A 10-bit ripple counter with a 256 kHz clock signal will have a maximum count (MOD number) of 1023, an MSB output frequency of 256 Hz, and a 50% duty cycle MSB signal. After 1000 input pulses, the counter count will be 3E8 in hexadecimal. A 4-bit ripple counter with a 20 MHz clock may not reach all states due to propagation delays between flip-flops. The maximum clock frequency before errors would be lower for a 6-bit versus 4-bit counter due to increased delays.

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    Digital System Design - UEC 612 Tutorial# 8

    Uploaded by

    Lakshit Gupta
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    A 10-bit ripple counter with a 256 kHz clock signal will have a maximum count (MOD number) of 1023, an MSB output frequency of 256 Hz, and a 50% duty cycle MSB signal. After 1000 input pulses, the counter count will be 3E8 in hexadecimal. A 4-bit ripple counter with a 20 MHz clock may not reach all states due to propagation delays between flip-flops. The maximum clock frequency before errors would be lower for a 6-bit versus 4-bit counter due to increased delays.

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    A 10-bit ripple counter with a 256 kHz clock signal will have a maximum count (MOD number) of 1023, an MSB output frequency of 256 Hz, and a 50% duty cycle MSB signal. After 1000 input pulses, the counter count will be 3E8 in hexadecimal. A 4-bit ripple counter with a 20 MHz clock may not reach all states due to propagation delays between flip-flops. The maximum clock frequency before errors would be lower for a 6-bit versus 4-bit counter due to increased delays.

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    12 views1 page

    Digital System Design - UEC 612 Tutorial# 8

    Uploaded by

    Lakshit Gupta
    A 10-bit ripple counter with a 256 kHz clock signal will have a maximum count (MOD number) of 1023, an MSB output frequency of 256 Hz, and a 50% duty cycle MSB signal. After 1000 input pulses, the counter count will be 3E8 in hexadecimal. A 4-bit ripple counter with a 20 MHz clock may not reach all states due to propagation delays between flip-flops. The maximum clock frequency before errors would be lower for a 6-bit versus 4-bit counter due to increased delays.

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    Digital System Design – UEC 612

    Tutorial# 8
    1. A 10-bit ripple counter has a 256-kHz clock signal applied: -
    (a) What is the MOD number of this counter?
    (b) What will be the frequency at the MSB output?
    (c) What will be the duty cycle of the MSB signal?
    (d) Assume that the counter starts at zero. What will be the count in hexadecimal after
    1000 input pulses?

    2. A four-bit ripple counter is driven by a 20-MHz clock signal. Draw the waveforms at the
    output of each FF if each FF has tpd of 20 ns. Determine which counter states, if any, will not
    occur because of the propagation delays.

    3. What is the maximum clock frequency fmax that can be used with the counter in above
    problem? What would fmax be if the counter is expanded to six bits?

    4. For the following state table:-

    (a) Draw the corresponding state diagram.


    (b) Identify redundant states, if any. Tabulate the reduced state table.
    (c) Draw the state diagram corresponding to the reduced state table

    6. Derive the state table and the state diagram of the sequential circuit below.
    Explain the function that the circuit performs.

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