IEEE INDICON 2015 1570173543

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FPGA Implementation of Second-Order Difference
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Plot for Epileptic Seizure Detection in EEG Signals
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10   Ardra Singh, A. Amalin Prince*
11   Electrical and Electronics Engineering Department
12   Birla Institute of Technology and Science Pilani,
13   K. K. Birla Goa Campus, Goa, India
14   *amalinprince@gmail.com
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17   Abstract—Field-programmable gate arrays (FPGAs) are to give accurate results. An algorithm utilizing EMD [8] and
18   being extensively used for a wide range of digital applications due second-order difference plot (SODP) [9] has provided an
to their flexibility and reprogrammability. This paper presents a average classification accuracy of 97.75% [6]. However, so
19   FPGA implementation of the second-order difference plot far, there are very few hardware implementations of seizure
20   (SODP) technique which can be used for the classification of ictal detection algorithms. A digital circuit capable of performing
21   and seizure-free electroencephalogram (EEG) signals. Empirical automatic real-time seizure detection can be used to filter out
22   mode decomposition (EMD) can break down an EEG signal into EEG data and transmit only ictal data for further analysis. This
23   simple oscillatory modes called intrinsic mode functions (IMFs). can immensely reduce transmission traffic and relieve trained
24   The hardware design developed takes a sampled IMF of an EEG
professionals from the time-consuming task of detecting
25   signal as input and generates its SODP while simultaneously
calculating the 95 percent confidence ellipse area of the SODP.
seizures by visual inspection of EEG signals. Also, hardware
26   implementation of a seizure detection algorithm can be used in
The ellipse area can be used as a parameter for detecting
27   epileptic seizures in EEG signals. The digital circuit was designed implantable chips allowing wireless closed-loop seizure
28   in the Vivado integrated development environment (IDE) using control [10-11].
29   Verilog hardware description language (HDL) and a Xilinx This paper presents a novel digital design that generates
30   Artix-7 xc7a100tcsg324 FPGA was used to verify operation of the the SODP of a time series and simultaneously calculates its
31   physical implementation. The hardware was tested on EEG data 95% confidence ellipse area. The design can be used in
32   made publicly available by the University of Bonn and the results
conjunction with a hardware implementation of the EMD
33   were found to be consistent with MATLAB simulations.
algorithm for developing an instrument for real-time seizure
34   Keywords—field-programmable gate array; epileptic seizure; detection. The use of SODP is not just limited to classifying
35   electroencephalogram signal; second-order difference plot; 95% EEG signals as epileptic and seizure-free [6]. It has been
36   confidence ellipse area applied to electrocardiogram (ECG) signals for detecting
37   congestive heart failure [12] and to center of pressure (COP)
38   signals for differentiating vibration frequencies [13]. The
I. INTRODUCTION
39   digital circuit was designed in the Vivado integrated
Epilepsy, a chronic neurological disorder marked by development environment (IDE) [14] using Verilog hardware
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unprovoked seizures, affects at least 65 million people in the description language (HDL). Verification of the hardware
41   world [1]. Anti-epileptic drugs prevent seizures by implementation was done on a Xilinx Artix-7 xc7a100tcsg324
42   suppressing excessive electrical activity of the neurons in the field-programmable gate array (FPGA). FPGA prototyping is
43   brain and have helped around two-thirds of all epilepsy popular because in addition to their speed and flexibility,
44   patients, while one-third remain unresponsive [2]. To benefit FPGAs can be reprogrammed any number of times.
45   the latter, new solutions are emerging from the field of
46   neuroengineering, many of which use electroencephalogram The rest of the paper is structured as follows. Section II
47   (EEG) signals for detecting epileptic seizures. The main idea presents the mathematical framework for SODP and ellipse
48   behind these solutions is to generate a feedback circuit which, area calculation. In section III, the proposed architecture for
upon detecting the onset of a seizure, delivers electrical FPGA implementation has been discussed. The results
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stimuli to the focal point resulting in the cessation of the obtained from simulation and implementation have been
50   compared and the hardware resource utilization has been
51   seizure [3].
tabulated in section IV. Finally, the conclusion has been drawn
52   For the purpose of seizure detection, various algorithms in section V.
53   based on wavelet analysis [4], time-frequency analysis [5] and
54   empirical mode decomposition [6-7] have been demonstrated II. MATHEMATICAL ANALYSIS
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56   A. Second-Order Difference Plot
57   978-1-4673-6540-6/15/$31.00 ©2015 IEEE
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 The second-order difference plot is a graphical method
originating from chaos theory that is used to study the amount
of variability present in a time series. The degree of variability
or chaos is an important attribute of complex nonlinear
systems and can be used for classifying them. The SODP of a
time series x(n) of length N plots consecutive rates X(n) and
Y(n) against each other, which are defined as [9]:
X(n) = x(n+1) – x(n) (1)
Y(n) = x(n+2) – x(n+1) (2)
B. Calculation of 95% Confidence Ellipse Area
For the purpose of quantifying the variability using SODP,
several parameters have been proposed, the central tendency
measure (CTM) [9] and the 95% confidence ellipse area being
the chief candidates [16-17]. The mathematics required to
calculate the latter is derived in [16] and [17]. First, we need
to calculate the rms values, Sx, Sy, and Sxy of X(n) and Y(n), as
shown:
Sx2 = {X(n)2}/N (3)
Sy2 = {Y(n)2}/N (4)
Sxy = {X(n)Y(n)}/N (5)
The major and minor radii, a and b, of the 95% confidence
ellipse are computed as:
a = 1.7321 * sqrt(Sx2 + Sy2 + D) (6)
b = 1.7321 * sqrt(Sx2 + Sy2 − D) (7)
The parameter D in (6) and (7) is given as:
D = sqrt{ Sx2 + Sy2 − 4(Sx2Sy2 − Sxy2)} (8)
The area of the ellipse, A_ellipse is simply the product of the
two radii multiplied by pi.
A_ellipse = π * a * b (9)
III. ARCHITECTURE FOR SODP AND ELLIPSE AREA
CALCULATION
A. Data Flow Graph
The computations required to generate the SODP and
calculate its 95% confidence ellipse area, as given in (1)
through (9), are modeled in a data flow graph (DFG) shown in
Fig. 1. As can be seen from the DFG, 10 add/subtract, 9
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Fig. 1. Data flow graph for ellipse area calculation
multiply/divide and 3 square root operations are required to
compute the final ellipse area. Although the total number of
operations can be reduced by carrying out some mathematical
simplifications, this begets intractably large bit widths of
intermediate variables. Keeping this trade-off in mind, the
flow depicted in Fig. 1 was adopted for the implementation.
B. Proposed Architecture
The proposed architecture for implementing the DFG
shown in Fig. 1 is represented in block diagram form in Fig. 2.
The data path has been has been split into 3 subunits, each of
which has its own control unit. The control units start and stop
the operation of the corresponding subunits by sending
appropriate flags. Subunit (i) generates the signals X(n) and
Y(n), which can be sent to an oscilloscope though a digital-to-
analog converter (DAC) for generating the SODP. Subunit (ii)
generates the mean square values of X(n) and Y(n), i.e. S x2,
Sy2, and Sxy. For implementation purposes we have fixed the
length of the time series, N as 1024. Thus division by N
becomes a simple right shift operation. Subunit (iii) performs
the remaining arithmetic for calculating the 95% confidence
ellipse area. All multiplications are carried out by embedded
digital signal processing (DSP) blocks. The square root
operation is carried out by a separate module which uses an
algorithm based on successive approximation. In this
algorithm, an initial trial root is iteratively increased or
decreased depending on whether its square is smaller or larger
than the input number. To preserve accuracy, 4 bits of the
decimal part of intermediate variables are kept and the rest are
discarded. This truncation helps avoid lengthy calculations
which slow down the entire design and leads to a very slight
loss in the accuracy of the final area.
 Fig. 2. Block diagram of the proposed architecture for FPGA implementation

their IMFs. This is corroborated by Fig. 3 as well as Table I.

IV. RESULTS AND DISCUSSION The ellipse areas obtained from FPGA implementation differ
For testing the functionality of the implementation, the from their simulated counterparts by 0.66% on an average.
publicly available EEG database provided by the University of This small lack of accuracy can be ascribed to bit width
Bonn, Germany [15] was used. The EEG database is divided truncation. The amount of different resources used in the
into 5 subsets: Z, O, N, F, and S. Subsets Z and O contain implementation of the design are listed in Table II. As can be
surface EEG recordings of healthy volunteers in a relaxed and seen, the entire design utilizes less than 1% of all the lookup
awake state with their eyes open and closed respectively. tables (LUTs) and registers available in the FPGA.
Subsets N and F contain intracranial EEG data of epilepsy The SODP area calculated by the digital circuit can be used as
patients recorded during seizure-free intervals. Subset N input for an artificial neural network classifier which can
contains recordings from the epileptogenic zone while subset detect the presence of an epileptic seizure. Upon detection, the
F contains those from the hippocampal formation of the seizure can be suppressed by delivering electrical stimuli to
opposite hemisphere of the brain. Seizure activity recorded the focal point.
from various sites comprises subset S.
TABLE II. RESOURCE UTILIZATION
Intrinsic mode functions (IMFs) of EEG data were computed
in MATLAB using the EMD codes given in [18]. SODPs of Resource Percentage
Utilization Available
Utilization
the first IMFs of different EEG signals, generated from Slice LUT as Logic 883 63400 1
simulation and implementation, are compared in Fig. 3. Figs. LUTs LUT as
3.a – 3.d correspond to EEG signals from subsets Z, O, N, and Memory
0 63400 0
F respectively which do not contain any seizure activity. Fig. Slice Register as
748 126800 1
3.e and Fig. 3.f on the other hand show the results for ictal Registers Flip Flop
EEG recordings belonging to subset S. The 95% confidence Register as
0 126800 0
ellipse areas of these SODPs are given in Table I. Latch
DSP
DSP48 20 240 8
TABLE I. COMPARISON OF SIMULATED AND IMPLEMENTED ELLIPSE Blocks
AREAS IOBs Bonded IOB 53 210 25
95% Confidence Ellipse Area
EEG Percentage
Signal MATLAB FPGA Error
Simulation Implementation V. CONCLUSION
Z001
(Fig. 3.a)
746.86 746.11 0.10 In this paper, the architecture of a digital circuit that
O001 generates the SODP of a time series and simultaneously
792.60 791.01 0.19 calculates its 95% confidence ellipse area has been presented.
(Fig. 3.b)
N001
57.33 58.71 2.41
The proposed architecture was implmented on a Xilinx Artix-
(Fig. 3.c) 7 xc7a100tcsg324 FPGA and the hardware results were
F001 compared with MATLAB simulations. The average error in
90.49 89.67 0.91
(Fig. 3.d)
S001
the ellipse area calculated on hardware was found to be less
425710.64 424877.31 0.20 than 1%. The design developed can be used in conjunction
(Fig. 3.e)
S010 with a hardware implementation of the EMD algorithm for
1128754.44 1126545.57 0.20
(Fig. 3.f) real-time seizure detection in EEG data. The design can also
be used to build instruments that quantify the amount of
variability present in other complex nonlinear systems.
The higher variability in EEG data recorded during epileptic
seizures is reflected in an increase in the span of the SODPs of

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 Fig. 3. Comparison of results from MATLAB simulations and FPGA implementation for seizure-free (a-d) and ictal EEG data (e-f)

ACKNOWLEDGMENT
The authors would like to acknowledge the Department of
Epileptology, University of Bonn for providing the EEG
database which was extensively used to test the efficacy of the
hardware design developed.
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