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Hardware Architecture of 8085 Microprocessor
Hardware Architecture of 8085 Microprocessor
There are totally six programmer accessible registers namely B,C,D,E,H,L that can either function as single 8-
bit register (such as B,C,D,E,H,L) or as 16-bit register pair such as BC , DE, HL. In case of register pair the
higher order byte is stored in first register (for example B-register in BC register pair) and lower order byte is
stored in second register (for example C-register in BC register pair). The HL register additionally functions as
MEMORY POINTER or DATA POINTER in MEMORY BASED DATA MOVEMENT INSTRUCTIONS.
The 8-bit registers W and Z are used for TEMPORARY DATA STORAGE when data is (i) moved between
registers (ii) Moved from internal registers to external data bus and vice-versa.
The 16-bit STACK POINTER(SP) is used to hold the address of TOP of STACK residing in external RAM. TOP OF
STACK is a STACK LOCATION where a RECENT PUSH OPERATION occurred. The type of STACK implemented is
LIFO(LAST IN FIRST OUT) , wherein the the element that is inserted into the LAST STACK location will be the
The Incrementer/Decrementer Address Latch is used to hold the INCREMENTED or DECREMENTED contents of
PC and SP.
The 8-bit BUFFERS (Lower order MULTIPLEXED Address and Data Bus Buffer[AD7-AD0] and Higher order Address
Bus Buffer[A15-A8]) acts as a DATA COMMUNICATION INTERFACE between INTERNAL DATA BUS and EXTERNAL
DATA BUS. The address bus (A15-A0) carries the content of PC and SP. The data bus (D7-D0) carries the content
of BC , DE , PSW , HL register pairs.
The 8-bit INSTRUCTION REGISTER is used to hold the OPCODE (HEXADECIMAL EQUIVALENT of an INSTRUCTION).
The INSTRUCTION DECODER is used for enabling a PARTICULAR INTERNAL COMPONENT of 8085 microprocessor
based upon the instruction received.
The MACHINE CYCLE ENCODER is used for providing information about the CURRENTLY EXECUTING MACHINE
CYCLE of an INSTRUCTION EXECUTION.
The 8-bit ALU is used to perform the following ARITHMETIC and LOGICAL OPERATIONS :
ARITHMETIC OPERATIONS :
8-bit and 16-bit ADDITION with and without CARRY
8-bit and 16-bit SUBTRACTION with and without BORROW
8-bit and 16-bit INCREMENT operation
8-bit and 16-bit DECREMENT operation
8-bit BINARY to BCD CONVERSION
LOGICAL OPERATIONS :
8-bit AND , OR , NOT , XOR operations
1-bit SET and RESET operation
8-bit ROTATE LEFT and RIGHT operations with and without CARRY.
The components of ALU are : (i) ACCUMULATOR (ii) TEMP (iii) 8-bit ALU (iv) FLAG
ACCUMULATOR :
8-bit REGISTER that acts as SOURCE or DESTINATION REGISTER in case of DATA TRANSFER INSTRUCTIONS
8-bit REGISTER that acts as SOURCE AND/OR DESTINATION REGISTER in case of DATA MANIPULATION (or
ARITHMETIC and LOGICAL) INSTRUCTIONS.
First SOURCE operand in case of DATA MANIPULATION INSTRUCTIONS.
TEMP :
8-bit REGISTER that acts as SECOND SOURCE operand in case of DATA MANIPULATION INSTRUCTIONS.
D7 D6 D4 D2 D0
S Z AC P CY
Combination of ACCUMULATOR and FLAG REGISTER is called PSW (Program Status Word).
ACCUMULATOR(8-BITS) FLAG(5-BITS)
FIG. PSW.
The TIMING and CONTROL circuitry is used for GENERATING TIMING , CONTROL and STATUS signals that is
required for operation of INTERNAL and EXTERNAL CIRCUITRIES of 8085 microprocessor IN SYNCHRONISM
The SERIAL CONTROL CIRCUITRY is used for SHIFTING the contents into and out-of of ACCUMULATOR and an
EXTERNAL REMOTE PERIPHERAL DEVICE as SEQUENCE of 1-BITs.
The INTERRUPT CONTROL CIRCUITRY is used for receiving EDGE AND/OR LEVEL TRIGGERED INTERRUPT
SIGNALS from EXTERNAL PERIPHERAL DEVICES and accordingly SEND an ACKNOWLEDGEMENT to the
interrupting device when the CPU branches to the corresponding Interrupt Vector Address. 8085 supports 5
hardware interrupts and 8 software interrupts.
8. ̅̅̅̅
𝑅𝐷 and ̅̅̅̅̅
𝑊𝑅 Active low signals
When RD signal is activated (ie.RD = 0) , the microprocessor reads a 8-bit data
from a selected memory location or Input port
When WR signal is activated (i.e. WR = 0) , the microprocessor writes a 8-bit data
into a selected memory location or output port.
Active during T2 and T3 states of each machine cycle.
9. ̅ , S0 ,
IO/𝑀 IO/𝑀 ̅ signal indicates whether 8085 microprocessor is currently accessing a
S1 memory location or I/O port. IO/𝑀 ̅ = 0 means 8085 is accessing a memory
̅
location and IO/𝑀 = 1 means 8085 is accessing a I/O port.
IO/𝑀̅ together with status signals S1 and S0 indicate what is the current machine
cycle executed by 8085 microprocessor.
Machine Cycle Status Signals
IO/𝑀̅ S1 S0
Bus Idle or No 0 0 0
Operation
Memory Write 0 0 1
I/O Write 1 0 1
Memory Read 0 1 0
I/O Read 1 1 0
INTR 1 1 1
Acknowledge
INTERRUPT SIGNALS
9. RST 5.5 – RST 8085 microprocessor supports 5 hardware interrupts.
7.5 , TRAP , Activating any one pin (TRAP or RST 7.5 or RST 6.5 or RST 5.5 or INTR) causes the
INTR , ̅̅̅̅̅̅̅
𝐼𝑁𝑇𝐴 microprocessor to complete its CURRENT INSTRUCTION EXECUTION.
Activation of INTA(INTerrupt Acknowledgement) signal by 8085 microprocessor
indicates it has accepted the INTR interrupt from the requesting device.
SERIAL I/O SIGNALS
10. SID , SOD SID refers to SERIAL INPUT DATA PIN
CONTENT IS FED INTO THE ACCUMULATOR FROM AN EXTERNAL DEVICE
THROUGH ITS MOST SIGNIFICANT BIT.
SOD refers to SERIAL OUTPUT DATA PIN
CONTENT IS FED OUT FROM THE ACCUMULATOR TO AN EXTERNAL DEVICE
THROUGH ITS MOST SIGNIFICANT BIT.
DMA (DIRECT MEMORY ACCESS) SIGNALS
11. HOLD , HOLD SIGNAL indicates that another microcontroller or microprocessor is
̅̅̅̅̅̅̅̅
𝐻𝐿𝐷𝐴 requesting the 8085 microprocessor to use its address bus , data bus and control
bus.
HLDA SIGNAL indicates the 8085 microprocessor has given permission to usage of
its buses to the requesting microcontroller or microprocessor
RESET SIGNALS
During T1 state , the 8085 microprocessor places the contents of program counter on the address bus.
The Higher Order Byte of PC placed in A15-A8 bus and Lower Order Byte of PC placed in AD7-AD0 bus.
The ALE signal is activated which separates the AD7-AD0 bus by enabling an external latch for holding
the lower order byte of PC.
During T2 state , the RD signal enables the memory location present in A15-A0 bus.
During T3 state , the opcode from the addressed memory location is placed in D7-D0 bus and the RD
signal is disabled.
During T1 state , the 8085 microprocessor places the contents of PC or SP or General Purpose Register
Pair on the address bus. The Higher Order Byte of PC or SP or the register pair placed in A15-A8 bus and
Lower Order Byte of PC or SP or the register pair placed in AD7-AD0 bus. The ALE signal is activated
which separates the AD7-AD0 bus by enabling an external latch for holding the lower order byte of PC or
SP or register pair.
During T2 state , the RD signal enables the memory location present in A15-A0 bus and 8-bit data is
placed in D7-D0 bus.
During T3 state , the 8-bit in D7-D0 bus is placed into a 8-bit register and the RD signal is disabled.
During T1 state , the 8085 microprocessor places the contents of SP or General Purpose Register Pair on
the address bus. The Higher Order Byte of SP or the register pair placed in A15-A8 bus and Lower Order
Byte of SP or the register pair placed in AD7-AD0 bus. The ALE signal is activated which separates the
AD7-AD0 bus by enabling an external latch for holding the lower order byte of SP or register pair.
During T2 state , the WR signal enables the memory location present in A15-A0 bus and data in the D7-
D0 bus.
During T3 state , the WR signal is disable the memory location , thereby terminating the write cycle.
I/O Read Machine Cycle :
In this machine cycle , 8085 microprocessor reads the data from an external input port.
During T1 state , the 8085 microprocessor places the input port address on A15-A0 bus.
During T2 state , the WR signal enables the Output Port present in A15-A8 bus or A7-A0 bus and 8-
bit data is placed in D7-D0 bus.
During T3 state , the 8-bit in D7-D0 bus is placed into the addressed output port and the WR signal is
disabled.
DAD instruction takes 10 T-states to execute. 4 T-states for opcode fetch and 6 T-states for adding the 16-bit
contents of HL register pair and given register pair. During those 6 T-states neither a memory or I/O read or
write operation takes place in the bus. These T-states are referred as BUS IDLE machine cycle. In case of DAD
instruction , RD and ALE signals are not activated.
RST 7.5 :
Second highest priority , Maskable , Positive Edge Triggered interrupt
Interrupt Vector address of RST 7.5 interrupt : 7.5 × 8 = 003CH (3CH is the hexadecimal equivalent of 6010)
Interrupt enabled and disabled using SIM , EI(Enable Interrupt ) , DI (Disable Interrupt) instructions.
Two ways to reset RST 7.5 interrupt :
Using SIM(Set Interrupt Mask) instruction
Using INTERNALLY generated ACKNOWLEDGEMENT signal.
RST 6.5 :
Third highest priority , Maskable ,Positive Level Triggered interrupt.
Interrupt Vector address of RST 6.5 interrupt : 6.5 × 8 = 0034H (34H is the hexadecimal equivalent of 5210)
Interrupt enabled and disabled using SIM , EI(Enable Interrupt ) , DI (Disable Interrupt) instructions.
RST 5.5 :
Fourth highest priority , Maskable , Positive Level Triggered Interrupt
Interrupt Vector address of RST 5.5 interrupt : 5.5 × 8 = 002CH (2CH is the hexadecimal equivalent of 4510)
Interrupt enabled and disabled using SIM , EI(Enable Interrupt ) , DI (Disable Interrupt) instructions.
INTR :
Fifth(Lowest) priority , Maskable , Positive Level Triggered Interrupt
No Vector Address Available ; Vector Address to be provided by Intel 8259 (Programmable Interrupt
Controller)
Interrupt enabled and disabled using SIM , EI(Enable Interrupt ) , DI (Disable Interrupt) instructions.
Example : Communication between INTEL 8279 (Programmable Keyboard and Display Controller) and
INTEL 8085 microprocessor or INTEL 8051 microcontroller.
On receiving the request , the microprocessor or microcontroller completes its current execution and
transfers the program control to the ISR of the corresponding requesting device.
The ISR performs the data transfer to the microprocessor or microcontroller and then returns back to its
main program at the point it was interrupted.
Example : Communication between INTEL 8259 (Programmable Interrupt Controller) and INTEL 8085
microprocessor or INTEL 8051 microcontroller
Example : Communication between INTEL 8237/8257 (Programmable DMA Controller) and INTEL 8085
microprocessor or INTEL 8051 microcontroller.
Example : Communication between INTEL 8218/8219 (Programmable Bus Controller) and INTEL 8085
microprocessor or INTEL 8051 microcontroller.
Design a microprocessor system for the 8085 microprocessor such that it should contain 16 KB EPROM
implemented using two 8 KB EPROM and a 4 KB RAM implemented using two 2 KB RAM using Absolute
decoding technique
SA of EEPROM 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000H
SA of EEPROM 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 2000H
EA of EPROM 2 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3FFFH
SA of RAM 1 0 1 0 X X 0 0 0 0 0 0 0 0 0 0 0 4000H
EA of RAM 1 0 1 0 X X 1 1 1 1 1 1 1 1 1 1 1 47FFH
SA of RAM 2 0 1 1 X X 0 0 0 0 0 0 0 0 0 0 0 6000H
EA of RAM 2 0 1 1 X X 1 1 1 1 1 1 1 1 1 1 1 67FFH
Design memory system for the 8085 microprocessor such that it should contain 1 KB EEPROM and 1KB RAM
using Linear Decoding or Partial Decoding.
A1 A A A A A A A A A A
Memory IC A15 A14 A13 A12 A11 Address
0 9 8 7 6 5 4 3 2 1 0
SA of EEPROM
0 X X X X X 0 0 0 0 0 0 0 0 0 0 0000H
EA of EPROM 0 X X X X X 1 1 1 1 1 1 1 1 1 1 3FFFH
SA of RAM 1 X X X X X 0 0 0 0 0 0 0 0 0 0 8000H
EA of RAM 1 X X X X X 1 1 1 1 1 1 1 1 1 1 83FFH