Half Adder

Data Flow:
module hAdata(

input A,

input B,

output C,

output S

);

assign S=A^B;

assign C=A&B;

endmodule

Test bench

module t1;

reg A;

reg B;

wire C;

wire S;

hAdata uut (

.A(A), .B(B), .C(C), .S(S)

);

Initial begin

A = 0;

B = 0;

#100;

A = 0;

B = 1;
#100;

A = 1;

B = 0;

#100;

A = 1;

B = 1;

end

endmodule
Half Subtractor
Data Flow :
module HSdata(

input X,

input Y,

output D,

output B

);

assign D=X^Y;

assign B=(~X)&Y;

endmodule

Test bench

module t2;

reg X;

reg Y;

wire D;

wire B;

HSdata uut (

.X(X), .Y(Y), .D(D), .B(B)

initial begin

X = 0;

Y = 0;

#100;

X=0

Y = 1;

#100;
 X = 1;

Y = 0;

#100;

X = 1;

Y = 1;

end

endmodule
Full Adder
Data Flow:
module FAbehav(

input a,

input b,

input cin,

output s,

output cout

);

reg s,cout;

always @(a or b or cin)

begin

if(a==0&&b==0&&cin==0)

begin

s=0;

cout=0;

end

else if(a==0&&b==0&&cin==1)

begin

s=1;

cout=0;

end

else if(a==0&&b==1&&cin==0)

begin

s=1;

cout=0;

end
 else if(a==0&&b==1&&cin==1)

begin

s=0;

cout=1;

end

else if(a==1&&b==0&&cin==0)

begin

s=1;

cout=0;

end

else if(a==1&&b==0&&cin==1)

begin

s=0;

cout=1;

end

else if(a==1&&b==1&&cin==0)

begin

s=0;

cout=1;

end

else

begin

s=1;

cout=1;

end

end

endmodule
Test bench

module t3;

reg a;

reg b;

reg cin;

wire s;

wire cout;

FAbehav uut (

.a(a), .b(b), .cin(cin), .s(s), .cout(cout)

);

initial begin

a = 0;

b = 0;

cin = 0;

#100;

a = 0;

b = 0;

cin = 1;

#100;

a = 0;

b = 1;

cin = 0;

#100;

a = 0;

b = 1;

cin = 1;

#100;

a = 1;
 b = 0;

cin = 0;

#100;

a = 1;

b = 0;

cin = 1;

#100;

a = 1;

b = 1;

cin = 0;

#100;

a = 1;

b = 1;

cin = 1;

#100;

end

endmodule
Full Subtractor
Behavioural Modelling:
module FSbehav(

input a,

input b,

input c,

output d,

output bo

);

reg d,bo;

always @(a or b or c)

begin

if(a==0&&b==0&&c==0)

begin

d=0;

bo=0;

end

else if(a==0&&b==0&&c==1)

begin

d=1;

bo=1;

end

else if(a==0&&b==1&&c==0)

begin

d=1;

bo=1;

end
 else if(a==0&&b==1&&c==1)

begin

d=0;

bo=1;

end

else if(a==1&&b==0&&c==0)

begin

d=1;

bo=0;

end

else if(a==1&&b==0&&c==1)

begin

d=0;

bo= 0;

end

else if(a==1&&b==1&&c==0)

begin

d=0;

bo=0;

end

else

begin

d=1;

bo=1;

end

end

endmodule
Testbench

module t4;

reg a;

reg b;

reg c;

wire d;

wire bo;

HSbehav uut (

.a(a), .b(b), .c(c), .d(d), .bo(bo)

);

initial begin

a = 0;

b = 0;

c = 0;

#100;

a = 0;

b = 0;

c = 1;

#100;

a = 0;

b = 1;

c = 0;

#100;

a = 0;

b = 1;

c = 1;

#100;

a = 1;
 b = 0;

#100;

a = 1;

b = 0;

c = 1;

#100;

a = 1;

b = 1;

c = 0;

#100;

a = 1;

b = 1;

c = 1;

end

endmodule