TERM PAPER FOR PHYSICAL ELECTRONICS ,NOVEMBER 2009
ZnO Nanowires and its applications: Field-Effect
Transistors(FETs)
Gursharan Singh Bhue and Udita Singh
Department of Electrical Engineering
Indian Institute of Technology Delhi
New Delhi - India
Abstract—ZnO Nanowires have become a prominent and wide
area of research for their excellent properties and wide range of
applications in the field of nanotechnology. ZnO is a promising
material for the realization and future of nanotechnology. ZnO
has a wide band-gap(3.37 eV), high excitonic binding energy and
high breakdown strength which makes it excellent material for
electronic and photonic devices, as well as for high-frequency
device applications. This paper presents an overview on ZnO
nanowire technology and its applications as Field-Effect Tran-
sistors (FETs) covering topics ranging from basic introduction
about ZnO, various ZnO nanowire-synthesis techniques and
nanowire properties to the device characteristics based on field
effect transistor configurations.
Index Terms− Field effect transistor (FET), nanowire, ZnO.
I. INTRODUCTION
N ANOWIRES are nanostructures with the diameter of the
order of a nanometre (1 nm). They are special structures
which have thickness or diameter in nanometre range and
an unconstrained length. At such scales, quantum mechanical
effects come into consideration and hence these wires are
also known as quantum wires. Nanowires can be classified
as metallic (e.g. Ni, Pt, Au), semiconducting (e.g. Si, ZnO,
InP, GaN, etc) and insulating (e.g. SiO2 , TiO2 ).
Semiconductor nanowires are very important research area
today primarily because of their special material properties and
wide range device applications. Nanowires form elementary
building blocks of nanoelectronic devices. Their applications
as field-effect transistors (FETs) have shown remarkable re-
sults. They operate at ultra-low power below microwatts and
a very high operation speed. Nanowires are characterized by
their high aspect (length to width) ratio of 1000 and even
more. They, therefore, are often called as one dimensional (1-
D) materials.
Among group II−VI semiconductors, Zinc Oxide (ZnO)
nanowires are extensively studied materials for their abundant
physical properties which makes it a versatile material for
a wide variety of device applications. Low-cost ZnO LEDs
could be used in traffic signals, outdoor displays, backlighting
in electronic displays, automobile brake lights, indicators on
electronic devices, biodetectors, and general lighting applica-
tions. ZnO has a number of material advantages over GaN,
[2] such as:
• A large exciton binding energy (60 meV compared with
26 meV for GaN).
1
• High resistance to radiation damage by high energy
radiation.
• Availability of high quality single crystal wafers.
• Wet chemical etching which results in simplified device
characteristics.
An alloy of ZnO with CdO, MgO, or BeO results in
obtaining a tunable bandgap. ‘’The bandgap can be changed
from 3 to 4.0 eV in Zn1 -xCdx O and Mgx Zn1 -xO alloy films
with small lattice mismatch. This makes it possible to realize
strainfree and highquality multiple quantum well device
structures. ZnO also has a high breakdown electric field of
2 × 106 V/cm and a large saturation velocity of 3.2 × 107
cm/s at room temperature.“ [2]
Section II describes the basics of ZnO structure and some
important facts. Section III discusses the various synthesis
techniques for ZnO nanowires. Section IV provides different
properties of ZnO nanowires. Section V discusses different
architectures of ZnO nanowires FET.Sections VI discusses
the ZnO NWFET characteristics.Section VII discusses the
final conclusions regarding the challenges and future of ZnO
nanowire technology.
II. Z N O STRUCTURE
ZnO has a stable wurtzite crystal structure. As shown
in the figure, the zinc atoms are tetrahedrally coordinated
with four oxygen atoms, which can be considered as two
interpenetrating hexagonal closepacked lattices of zinc and
oxygen.
Some key facts about ZnO crystal structure are:
1) ZnO has non-centrosymmetric (i.e. lacks inversion sym-
metry) wurtzite structure and therefore has properties
like piezoelectricity and pyroelectricity.
2) At room temperature, ZnO has direct wide band gap
energy of 3.37 eV.Advantages associated with a large
band gap include higher breakdown voltages, ability to
sustain large electric fields, lower electronic noise, and
high-temperature and high-power operation.
3) The lattice parameters of wurtzite ZnO are a = b =
3.250 and c = 5.206 The specific gravity is 5.72 g/cm3 ,
which corresponds to 4.21 × 1022 molecules per cubic
centimeters.
TERM PAPER FOR PHYSICAL ELECTRONICS ,NOVEMBER 2009
Fig. 1. ZnO Wurtzite crystal structure [1]
4) The ionic radii on Zn2+ and O2 are 0.60 and 1.38 ,
respectively, corresponding to a ZnO distance of 1.972
.
III. SYNTHESIS OF Z N O NANOWIRES
Synthesis techniques for nanowires are very crucial. They
should be reproducible to produce high quality nanowires for
nanoelectronic devices. They determine the material crystal
structure and physical properties of nanowires.
These primary techniques for synthesis can be classified into
two main categories: Vapour-Phase growth and Solution-Phase
growth.
A. Vapour-Phase Growth
In this category, Chemical Vapour Deposition (CVD) meth-
ods are utilized for nanowire synthesis via vapour-liquid-
solid (VLS) or vapour-solid (VS) mechanisms. Direct ther-
mal evaporation, carbon thermal reduction, metal-organic, and
laser-assisted synthesis are some of the variations of CVD
approaches that have been developed for synthesising high
quality ZnO nanowires.
1) VLS Growth Mechanism: In VLS growth mechanism,
catalytic particles or clusters, such as Au or Ag, are deposited
on the growth substrate which then serves as seeding sites for
nanowire growth. Zn vapour dissolves into the catalysts and
forms alloy droplets at high temperature. At supersaturaion, Zn
crystal precipitates out at the interface with the substrate and
forms ZnO nanowire. As shown in fig 2(a), Au particles can
be seen at one of the ends of nanowires indicating tip-growth
VLS mechanism. [3]
2) VS Growth Mechanism: It is a self-catalytic process in
which the evaporated Zn vapour condenses into the substrate
and form the nucleation sites for further growth.
ZnO nanowires are vertically aligned by lattice matching
with the substrate material during Vapour Phase growth. ZnO
having hexagonal lattice constants a = 3.249 and c= 5.207 has
2
Fig. 2. (a) ZnO nanowires synthesized by CVD method. (Inset) catalytic
particles at the ends of individual nanowires, indicating VLS tip growth
mechanism. (b) Vertically aligned nanowires are grown on lattice matched
a-plane sapphire substrate.[3]
a strong growth direction along c-axis [0001]. Its (0001) plane
has a tendency to form a good epitaxial interface with a-plane
of sapphire (with a = 4.785 and c = 12.991). GaN, SiC,
Si and ZnO-film-coated substrates are some other epitaxial
substrates utilized to match with the ZnO (0001) crystal plane.
ZnO nanowires have been reported to grown on various
substrates:[5]
1) an undoped ZnO film with Au catalyst (denoted as
AuZnO) or without Au catalyst (denoted as ZnO)
2) a gallium-doped ZnO film with Au catalyst (denoted as
AuGZO) or without Au catalyst (denoted as GZO);
3) an aluminum-doped ZnO film with Au catalyst (denoted
as AuAZO) or without Au catalyst (denoted as AZO);
4) an Au-coated sapphire (denoted as Ausapphire) sub-
strate.
Key points of Vapour-Phase growth techniques:
1) ZnO produced from such methods are largely single
crystal structures.
2) These nanowires may generally have lengths greater than
10 µm.
3) These are cost-intensive methods.
4) Production capacity and rate are generally low.
B. Solution-Phase Growth
Polycrystalline ZnO nanowires are synthesized by direct
electrochemical deposition into a prefabricated hexagonally
TERM PAPER FOR PHYSICAL ELECTRONICS ,NOVEMBER 2009 3

ordered anodic aluminium oxide (AAO) template followed by uses ZnO nanowires as a prominant material.
thermal oxidation. AAO is soaked into zinc nitrate solution and
urea mixture at 80o C for up to 48 hrs., followed by thermal
heat treatment to synthesize ZnO nanowires in Sol−gel
process. Hydrothermal process, microwave irradiation and
ultrasonic irradiation methods are some other methods based
on wet-chemical approaches for ZnO nanorods synthesis.
Vertically aligned growth of ZnO nanorods is observed by
ultrasonic sonochemical method. [3]

Key points of Solution-Phase growth techniques:

1) ZnO produced from such methods are largely polycrys-
talline.
2) These nanowires may generally have short lengths
smaller than 10 µm.
3) These are cost-efficient methods and generally operate
at low temperatures.
4) Production capacity and rate are high resulting in bulk
production of nanowires.
Currently, pulsed laser deposition (PLD) is used to deposit
thin films of ZnO on a variety of substrates. PLD consists
of a vacuum chamber containing a target material (Zn) and
substrate(glass and sapphire), mounted approximately 5 cm
from the target. A KrF Excimer laser (λ = 248 nm) ablates
the target material at high energy (350 mJ) and repetition (6
Hz) in the presence of ambient oxygen to form a plasma. The
target material is then deposited on the substrate. The ambient
oxygen also aids in depositing oxides.[4]

IV. PROPERTIES OF Z N O NANOWIRES
The device applications of nanowires are strictly depen-
dent on the intrinsic material properties. Therefore, it is of
prime interest to study fundamental physical properties of
ZnO nanowires for getting insight into their applications in
nanoelectronic devices.
A. Optical Properties
ZnO is a natural n-type semiconductor. Defects like oxygen
vacancies and zinc interstitials gives rise to electron donors.
These defects form impurity bands with shallow donor
levels around 30-60 meV and deep levels around 0.7-2.3
eV, below the conduction band edge. These impurity states
have been confirmed by various spectroscopy techniques
such as photoluminescence (PL), cathodoluminescene, and
electroluminescence.” The PL spectra of ZnO nanowires show
band-edge emission peak at ∼3.37 eV and defect-related
emission at ∼2.5 eV “.[3] Fig 3(a) shows comparison of
band-edge emissions from nanowires with different diameters.
The emission from nanowires of 200 nm diameters shows a
strong peak at 3.362 eV attributed to donor-bound excitons
(labeled as D-X), whereas thinner nanowires ( 15 nm) shows
dominant emission peak at 3.366 eV. Increased surface to
volume ratio leads to surface bound exciton (SX), which
is the reason for this shift. Efficient excitonic emission
at temperatures well above room temperature under low
excitation intensity is ensured by larger exciton binding
energy. Short wavelength optoelectronic applications thus
Fig. 3. (a) Band-edge emissions of ZnO nanowires of two different diameters.
(b) Temperature dependent conductivity showing two types of conduction
mechanisms: Arrhenius-type thermal activation for higher temperatures and
hopping conduction mechanism for lower temperature ranges. [3]
B. Electrical Properties
The electrical properties of ZnO nanowires are influenced
by the defect energy levels. It has been shown that impurity
band splits into two bands: a lower D band which is formed by
singly charged donors and a relatively wider upper D− band
with neutral donors. The Fermi-levels rests in the lower D
band. To gain insight into the intrinsic conduction in a single
ZnO nanowire with low resistance ohmic contacts, electrical
measurements are performed with a wide temperature range
to reveal the temperature dependent conductivity as shown in
fig 3(b)
Three distinct activation and hopping contributions with
discrete characteristic activation energies are observed.
• Above about 100 K, the charge transport mechanism is
dominated by the thermal activation of electrons from the
Fermi level, µ, to the conduction band.
• Between approximately 20 and 100 K, the charge trans-
port mechanism is due to the activation of electrons from
µ to the upper impurity (D− ) band.
• Between approximately 5 and 20 K, the charge transport
mechanism arises from the nearest-neighbor hopping
conduction within the lower impurity (D) band.
TERM PAPER FOR PHYSICAL ELECTRONICS ,NOVEMBER 2009 4

The temperature behavior of σ(T) between 100 and 20

K reveals that the intrinsic electrical-transport mechanisms
through individual ZnO NWs are due to a combination of
the thermal activation conduction and the nearest-neighbor
hopping conduction processes.
As fitted in the linear Ln σ versus T−1/4 plot [Fig.
3(b) inset], the hopping conductivity is expressed as σ ∝
exp(?T0 /T )1/(d+1) , where d is the dimensionality and T0
= βα3 /kB g(EF ) is the characteristic temperature, where α
is the inverse Bohr radius, g(EF ) is the density of states at
Fermi level, and β = 1.5. Such unique electrical conduction
behaviors can be explained in terms of the intricate material
properties (in particular, the presence of moderately high
concentrations of n-type defects accompanied with a slight
self-compensation) in natively doped ZnO NWs.[3]

C. Electrode and Nanowire Interface

Metal and semiconductor interface plays an important role
in determining transport behaviour and device performance.
Titanium (Ti) with a work function of ∼4.33 eV, which
is close to the ZnO electron affinity of ∼4.35 eV, is often
selected as the adhesive layer to make ohmic contact with
n-type ZnO to reduce the contact energy barrier. Studies
show that annealing metal contacts at high temperatures
(425o C−600o C) in O2 or H2 environment is effective to
compensate the interface defects and the defects in the gate
Fig. 4. (a) PL spectra of (green curve) nondoped nanowire, (red) doped before
dielectric [3], giving rise to better device ON/OFF ratio and annealing, and (blue) doped after annealing. (b) p-type Ids − Vg curves [3]
electron mobility.

V. ARCHITECTURE OF Z N O NANOWIRE FET

D. Doping in ZnO
Due to internal defects, ZnO nanowires are natively n-type
semiconductors. However to obtain higher donor concentra-
tion, one can introduce extrinsic dopants like Mg, Al, Ga,
In, and Sn. Efficient techniques to synthesize p-type ZnO
nanowires is still a challenging research area. The difficulties
in p-type ZnO nanowire synthesis can be attributed to two
main reasons:
• The first is due to the presence of self-compensating
mechanisms due to native defects.
• The second being the limited solubility of impurity atoms
in ZnO.
”One of the recent methods to synthesize p-type ZnO nanowire
is by introducing phosphor(P) as extrinsic acceptors. Phospho-
rus pentoxide (P2 O5 ) is used as a dopant source mixed with
ZnO/graphite powder, and synthesized P doped ZnO in a CVD
apparatus. Following an annealing process, P:ZnO nanowires
demonstrate p−type conduction behavior which is confirmed
by the evolution of acceptor-bound exciton (AX) peaks in
PL measurement [Fig. 4(a)]“[3]. The Ids − Vds and Ids − Vg
characteristics of P:ZnO nanowires shown in Fig. 4(b) clearly
show that negative gate voltage enhances the conductance of
ZnO nanowire and further manifests the p-type semiconductor
behavior.
Nanowires by virtue of being a good conductor and a single
crystalline structure makes it best for application in the field
effect transistors and so several research projects are ongoing
in making it possible. The fabrication of nanowire based FET
remains a vital and paramount task to make the nanoscale
electronic devices based on nanowires feasible. In addition
to the source and drain electrodes being served by a pair of
leads patterned onto the two ends of a nanowire channel in
the FET configuration, the conduction in a nanowire can also
be switched on/off by introducing transverse electric fields
using a weakly capacitively coupled terminal. Properties of
Zinc oxide nanowires such as easy to synthesis, naturally
n-type semiconductor and easy contact to metal gives it an
advantage over others to be utilized as channel FETs.
Different gate structures have been fabricated and every
model has some advantages and some limitations. The four
major types of gate configurations are:
1) Back-gated FET
2) Top-gated FET
3) Side-gated FET
4) Vertically-surrounding FET
The back-gate gate structure is apparently the most popular
among these gate structures which have been used to fabricate
many nanowires by lithography process. Although, the back-
gate cannot be used to control devices in case of integrated
TERM PAPER FOR PHYSICAL ELECTRONICS ,NOVEMBER 2009
devices since the gate electrodes are heavily doped substrates
and the high-energetic (greater than 30 keV) electron beams
can damage the nanowires in the electron-beam lithography
process. Also, since only one device per process is fabricated,
the device yield is very low.
Hence, fabrication technique of top-gate nanowire-based
FETs by a photolithography process is practised. Top-
gate ZnO nanowire-based FETs were fabricated by a
photolithography process. ZnO nanowires were utilized as
channels of top-gate FETs, because these oxide nanowires
have their several merits [6] .
Fig. 5. Back-gated ZnO NWFET on SiO2 /p++ Si substrate. [3]
A. Back-Gated FET
The back gate configuration(fig 5.) is the most basic and
traditional structure. Most nanowire-based FETs have been
based on back-gate types, and fabricated by an electron-beam
lithography process.
Place a nanowire on a Si back gate under a SiO2 dielectric
layer with source and drain electrodes attached at the two
ends in order to design back gated FET. Due to heavy doping
of substrates which are used as gate electrodes, it is very
difficult to individually control each device in backgated FET.
The typical field-effect mobility of back-gated device falls in
the range 3−80 cm2 /V−s. and the ON/OFF ratio is around
104 − 106 .
The back gate capacitance is estimated as
Cback = 2πr 0 Lnw /ln(2h/rnw ) based on the cylinder-on
plate model ,
where Lnw is the nanowire channel length,
rnw is the nanowire radius,
h is the thickness of dielectric, and
r is the relative dielectric constant of the gate dielectric.
Limitations:
• It lacks precision control of individual channel segments
and poses difficulty for device integration.
• To have greater control and effective gate operation,
dielectric layer should be thin. But thin dielectric results
in large leakage current. This problem can be overcome
by using high-k dielectric material.
For example,
5
• HfO2 dielectric with much higher k value (k = 16)
than SiO2 (k = 3.9) can be prepared readily on p++ Si
substrate.
• Al2 O3 and organic polymer have also been used as an
effective gate dielectric layer.[3]
B. Top-Gated FET
To overcome the problem of lack of control of individual
channel segment of backgated FET, top gated FET structure
has been developed. Topgated FET is fabricated by the process
of photolithography. Due to localised top−gated electric field,
there is precise control. It has comparatively higher value of
ON/OFF ratio ( ∼ 107 ) as compared to backgated FET. The
source−drain contacts are first patterned and then followed by
a gate dielectric deposition. The top gate capacitance can be
Fig. 6. Fabrication procedure of a top-gate nanowire FET. (a) Formation
of marker patterns on a SiO2 /Si substrate, (b) dispersion of nanowires, (c)
formation of source and drain electrodes, and (d) formation of gate oxide and
electrode.[6]
estimated as
Ctop = 2πr 0 Lg /ln(rg /rnw )
where Lg is the length of nanowire under gate dielectric,
rnw is the nanowire diameter, and
rg is the outer diameter of surrounding dielectric layer.
Advantages:
Fig. 7. The SEM image of a top-gate nanowire FET fabricated by
photolithography process.
• By using high-k material and adjusting the rg /rnw ratio,
large gate capacitance can be achieved and thus improved
transconductance.
• ON/OFF ratio is significantly better than the common
back gate configuration.
TERM PAPER FOR PHYSICAL ELECTRONICS ,NOVEMBER 2009 6

C. Side-Gated FET VI. Z N O NWFET CHARACTERISTICS

In side-gated FET, metallic (Cr) gate electrodes are A. n-type Depletion-Mode FET
made just a few nanometres away from the suspended
ZnO nanowires with air as the dielectric in the gap. ”The
field-effect mobility close to 1000 cm2 /V−s, which is the
highest reported value among nonpassivated ZnO NWFETs.
Its ON/OFF ratio is around 106 “ [3].

Fig. 9. Current voltage characteristics of ZnO n-type Depletion-Mode FET[7]

From the source−drain current versus gate voltage (Ids −Vg )

curve for ZnO NWFET, it can be inferred that positive Vg
induces higher channel conductance as for typical n-type FET
behaviour.
Vgt is the gate threshold voltage at which current is sup-
pressed to an OFF state. A depletion-mode FET behavior is
indicated by the negative Vgt value, i.e., device is in the ON
state at zero applied gate voltage. [3]
Fig. 8. (a) Vertically oriented ZnO nanowires are grown from SiC substrate The electrical characteristics of ZnO NW-FETs are sum-
with a conformal coating of SiO2 as the gate dielectric and Cr as the gate marized in Figs. 9 and 10. Figures 9(a) and 9(b) shows
electrode. (b) Additional SiO2 layer is deposited and later planarized for top
electrode contact patterning [3]. (c) ZnO nanowires are grown in a rodlike the source−drain current versus voltage IDS -VDS and
AAO template for making surrounding gate NWFET [3]. source−drain current versus gate voltages IDS -VG for an n-
channel D-mode FET using ZnO nanowires grown on an Au-
Advantage: Excellent gate modulation efficiency is achieved coated sapphire substrate. The IDS -VDS curves fig. 9(a) of an
by small gate insulator (air gap) thickness ( ∼26 nm).. n-channel D-mode FET shows linear behaviour at low biases
Limitation: The reproducibility in its fabrication due to the and saturation at high biases. The IDS -VG curves fig. 9(b)
difficulty of making exact alignment. show that the threshold voltage Vth is −4.14 V, indicating n-
channel D-mode behavior. On/off current ratio as large as 105
is seen by the IDS -VG plot in the semilogarithmic scale. [7]
D. Vertical Surrounding FET
B. n-type Enhanced Mode FET
Vertically oriented NWFET increases the device number
per unit area and achieve ultrahigh integration density of
FET devices. In fig 8 various stages of VSG-FET fabrica-
tion are shown. Vertically grown ZnO nanowires have been
successfully fabricated using DC and pulsed electrodeposition
methods in a highly ordered anodic aluminum template. An
evaporated layer of titanium on one side of the template serves
as the working electrode in a standard three electrochemi-
cal cell. It is found that pulsed electrodeposition grows Zn
nanowires with a much higher filling factor and uniformity.
The ZnO nanowires were formed by thermally oxidizing the
Zn nanowires.
The fabrication of VSG-FET requires strenuous procedures;
however, it will serve as the building blocks for nanoscale
memory and logic devices.
Fig. 10. Typical current voltage characteristics of ZnO n-type Enhancement-
Limitation : Till date manufacturing large scale surrounding Mode FET[7]
gate NWFETs is an unsolved problem but, the success in
fabricating vertical nanowire devices holds promising potential The IDS -VDS and IDS -VG curves shown in Fig. 10 exhibit
for Tera-level packing density of nano electronic devices. the enhanced-mode device behavior with a positive threshold
TERM PAPER FOR PHYSICAL ELECTRONICS ,NOVEMBER 2009
gate voltage around +10.85 V. Enhancement mode behaviour
can be attributed to the high density of surface states and in-
terface defects which arise due to increased surface roughness.
Fig. 10(a) gives the output characteristic IDS -VDS .In the IDS -
VG curves fig. 10(b) for FETs using ZnO nanowires grown
on an Au-catalyst-free ZnO film, the threshold voltage Vth is
+10.85 V, indicating n-channel E-mode behavior. The IDS -VG
plot in the semilogarithmic scale shows an on/off current ratio
as large as 106 . [7]
C. Surface Passivation
Fig. 11. (a) IDS VDS and (b) IDS VG curves of a FET device made from
smooth ZnO nanowires before and after passivation.[5]
In order to improve the performance of ZnO NWFET, it
is critical to enhance the carrier mobility in the nanowire
channel. Passivating the surface of ZnO nanowires, is one
of the effective method. Metal oxide materials have a large
amount of surface defects, predominantly oxygen vacancies,
which serve as the binding sites in chemisorptions processes.
These active binding sites contribute to the scattering and
trapping of charge carriers .
There are mainly two methods that have been used to
compensate the surface defect states.
• First, post-annealing in N2 , H2 , O2 , or ozone has
shown improvements in forming ohmic contact with ZnO
7
Fig. 12. (a) IDS VDS and (b) IDS VG curves of a FET device made from
rough ZnO nanowires before and after passivation. [5]
nanowires and in passivating the surface. The nanowire
surface encounters a rearrangement of crystallography
orientation at high temperature in gas ambient, yielding
a reduction of surface defects.[3]
• Surface coating such as with SiO2 , SnO2 , and organic
polymers (polyimide and PMMA ) has shown signif-
icantly increased carrier mobility. Surface coating can
completely isolate the nanowire surface to avoid oxygen
adsorption.[3]
The current-voltage characteristics have shown significant
improvement after passivation as is shown by fig. 11 and 12.
VII. C ONCLUSION
In the evolving field of nanotechnology, where the size
of devices is gowning down, nanowires have become an
important and promising research area. Nanowires fabricated
to form Field Effect Transistors (FETs),are the elementary
building blocks of future nanoscale devices. Among metal-
oxide semiconductors, ZnO ia a very important and versatile
material because of its favourable properties: good trans-
parency, high electron mobility, wide bandgap, strong room-
temperature luminescence, etc. ZnO NWFETs are currently
being researched and have been fabricated in various gating
TERM PAPER FOR PHYSICAL ELECTRONICS ,NOVEMBER 2009 8

configurations. Back, top, side, and surrounding gate archi-

tectures have been developed for the goal of performance
improvements and high integration density. ZnO NWFET can
be implemented into either n-type depletion or enhanced-mode
operations that are both essential in logic circuit construction.
Despite the technological advancements in the field of ZnO
nanowires synthesis and fabrication in NWFETs, still a lot of
work has to be done. There are still various research challenges
in this field that motivates for further study of the material. One
such interesting and important challenge is the synthesis of p-
type ZnO. Although methods have been developed to display
p-type ZnO behaviour but still reproducible and controllable
p-type doping has not been developed so far. Other important
issue concerns the conduction mechanism in ZnO and how is it
influenced by various physical parameters like impurity states,
surface contribution, quantum effects, etc. Thus with the com-
prehensive study of the physics of ZnO and its properties, one
can develop cutting-edge ZnO nanowire technology which can
revolutionise the field of nanotechnology and nanoelectronics.

R EFERENCES
[1] http://en.wikipedia.org/wiki/File:Wurtzitepolyhedra.png
[2] Steve J. Pearton, Fellow, IEEE, David P. Norton, Li-Chia Tien, and
Jing Guo. ”Modeling and Fabrication of ZnO Nanowire Transistors ”.
IEEE TRANSACTIONS ON ELECTRON DEVICES, . VOL. 55, NO. 11,
NOVEMBER 2008.
[3] Pai-Chun Chang and Jia Grace Lu ”ZnO Nanowire Field-Effect Transis-
tors ”. IEEE TRANSACTIONS ON ELECTRON DEVICES, . VOL. 55,
NO. 11, NOVEMBER 2008.
[4] Nicole Staszkiewicz, Electrical Engineering, University of Florida ”Syn-
thesis and Characteristics of ZnO Nanowires”. NNIN REU Site: Solid
State Electronics Laboratory, University of Michigan, Ann Arbor Principal
Investigator Mentor: Dr. Jamie D. Phillips, Electrical Engineering and
Computer Science, University of Michigan Ann Arbor .
[5] Woong-Ki Hong, Gunho Jo, Soon-Shin Kwon, Sunghoon Song, and
Takhee Lee ”Electrical Properties of Surface-Tailored ZnO Nanowire Field-
Effect Transistors ”. IEEE TRANSACTIONS ON ELECTRON DEVICES,
. VOL. 55, NO. 11, NOVEMBER 2008.
[6] Kihyun Keem, Jeongmin Kang, Changjoon Yoon, Donghyuk Yeom,
Dong-Young Jeong, Byung-Moo Moon, and Sangsig Kim ”A fabrication
technique of top-gate nanowire FETs by a photolithography process” P-
NDEV12 Nanodevices . MNE06 Micro- and Nano- Engineering
[7] Woong-Ki Hong, Dae-Kue Hwang, Il-Kyu Park, Gunho Jo, Sunghoon
Song, Seong-Ju Park, Takhee Lee, Bong Joong Kim, E A. Stach ”Realiza-
tion of highly reproducible ZnO nanowire field effect transistors with n-
channel depletion and enhancement modes” Birck Nanotechnology Center,
Birck and NCN Publications, Purdue Libraries. Year 2007.