FIEE UNMSM

MULTIPLICACION, USANDO SUMAS SUCESIVAS

Factores de 4 bits.
Se utilizó la tarjeta cyclone 4.

Reset para nueva multiplicación, puls3 para mostrar multiplicación

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FIEE UNMSM

CODIGOS:

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity aplic_producto is

port(clk,reset,puls3,puls1,puls2:in std_logic;

display: out std_logic_vector(7 downto 0);

selector: out std_logic_vector(3 downto 0));

end aplic_producto;

architecture solucion of aplic_producto is

component anti_rebote

port(clk,entrada: in std_logic;

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FIEE UNMSM

salida: out std_logic);

end component;

component contador0_9 is

port(reset,clk :in std_logic;

conta: buffer std_logic_vector(3 downto 0));

end component;

component maq_producto

port (clk,clear_load,dec_suma,done:in std_logic;

z_sal: out std_logic;

input_M,input_N: in std_logic_vector(3 downto 0);

sal_u,sal_d: out std_logic_vector (3 downto 0));

end component;

component control_producto

port(clk,z_sal,producto,reset: in std_logic;

clear_load,dec_suma,done: out std_logic);

end component;

component diplay_4

port (clk: in std_logic;

E0,E1,E2,E3 : in std_logic_vector(3 downto 0);

display: out std_logic_vector(7 downto 0);

selector: out std_logic_vector(3 downto 0));

end component;

signal pulso1,pulso2,pulso4,pulso3,clear_load,dec_suma,done,z_sal: std_logic;

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FIEE UNMSM

signal input_M,input_N,E0,E1: std_logic_vector(3 downto 0);

begin

U0:anti_rebote port map(clk,puls1,pulso1);

U1:anti_rebote port map(clk,puls2,pulso2);

U2:contador0_9 port map(pulso3,pulso1,input_M);

U3:contador0_9 port map(pulso3,pulso2,input_N);

U4:maq_producto port map(clk,clear_load,dec_suma,done,z_sal,input_M,input_N,E0,E1);

U5:control_producto port map (clk,z_sal,pulso4,pulso3,clear_load,dec_suma,done);

U6:diplay_4 port map (clk,E0,E1,input_N,input_M,display,selector);

U7:anti_rebote port map(clk,reset,pulso3);

U8:anti_rebote port map(clk,puls3,pulso4);

end solucion;

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