Power PDF

Rapid Adoption Kit - Innovus Low-Power Design Flow
Cadence Design Systems, Inc.
Rapid Adoption Kit (RAK)
Innovus Low-Power Design Flow

CPF Implementation
Tool Version – Innovus Implementation System 18.10

Note: Testcase database, Scripts and references can be found at the ‘Attachments’ and
‘Related Solutions’ sections below the PDF on https://support.cadence.com
COPYRIGHT © 2018, CADENCE DESIGN SYSTEMS, INC.

ALL RIGHTS RESERVED. 1
Table of Contents
Module 1: Getting Started .................................................................................................................. 4

Lab 1-1 Introduction to the Labs ......................................................................................................... 5
Multiple Supply Voltages (MSV) and Power Shut Off (PSO) ......................................................... 5
Flow Setup/Environment Scripts ...................................................................................................... 6
Implementation Scripts..................................................................................................................... 6
Flow Directory Structure .................................................................................................................. 7
Lab 1-2 Setting Up the Workshop....................................................................................................... 8
Foundation Flow Step: run_init.tcl ................................................................................................... 8
CPF ................................................................................................................................................... 8
Lab 1-3 MMMC ................................................................................................................................. 10
Loading and Committing CPF to the Innovus System.................................................................... 10
Lab 1-4 Floorplan, Power-Switch Insertion and PPPR ...................................................................... 12
Defining Power Domain Physical Attributes ................................................................................. 12
Power Domain Floorplan ................................................................................................................ 14
Power Switch Insertion................................................................................................................... 14
Power Planning ............................................................................................................................. 155
Lab 1-5 Generating DB by run_init.tcl ............................................................................................. 17
Module 2: Foundation Flow Step: run_place.tcl ..................................................................................... 18
Lab 2-1 Creating a Domain-Aware Placement ................................................................................. 19
Lab 2-2 Optimizing the Domain-Aware preCTS .............................................................................. 21
Always-on Buffering ...................................................................................................................... 21
DB Generated by run_place.tcl ...................................................................................................... 22
Module 3: Foundation Flow Step: run_cts.tcl ......................................................................................... 23
Lab 3-1 Secondary Power Pin Routing............................................................................................. 24
Lab 3-2 Running the Domain-Aware Clock Tree Synthesis ............................................................. 26
DB Generated by cts step ............................................................................................................... 26
Module 4: Foundation Flow Step: run_postcts_hold.tcl ....................................................................... 288
Lab 4-1 Running the Domain-Aware PostClock-Tree Synthesis .................................................... 299
DB Generated by run_postcts.tcl .................................................................................................. 299
Module 5: Foundation Flow Step: run_route.tcl ..................................................................................... 30
Lab 5-1 Routing the Design ............................................................................................................ 311
DB Generated by run_route.tcl ..................................................................................................... 311
Highlighting the Results ............................................................................................................... 311
Module 6: Foundation Flow Step: run_postroute.tcl ............................................................................ 355
Lab 6-1 Running a Domain-Aware Postroute Optimization ................................................... 36
DB Generated by run_route.tcl ............................................................................................... 366
Workshop Summary ..................................................................................................................... 377
Workshop Limitation.................................................................................................................... 377
RAK Database ................................................................................Error! Bookmark not defined.7

Module 1: Getting Started

Lab 1-1 Introduction to the Labs
Objective: To introduce the concepts and materials in the workshop.
In this lab, Innovus is used to implement and practice Multi-Mode-Multi-Corner (MMMC) on the simple
DMA design through the Cadence® Low Power Design Foundation Flow by using CPF. This tutorial
helps you to take advantage of CPF to implement designs with multiple supply voltage (MSV) and power
shut-off (PSO) architecture and show you how to use the LP foundation flow. This workshop requires
the Innovus license with LP options to run.
The DMA gate-level netlist was generated by Cadence® RTL Compiler (RC) using the same CPF. There
are separate LABs for the frontend parts such as RC and CLP.
Multiple Supply Voltages (MSV) and Power Shut Off (PSO)
Cadence Innovus® Low Power Design Flow supports advanced power management techniques such as
multiple power domains with power shut-off (PSO) scheme, which can only be implemented at the
physical level (post synthesis). By adopting CPF, the designer’s intent for advanced power management
techniques can be captured as design and technology-related power constraints in a single file format for
use throughout the RTL and GDSII design flow including verification, validation, synthesis, test,
physical implementation, and signoff analysis.
In this workshop, CPF captures the following implementation techniques and will be loaded and
committed before power planning in this low power design flow. The explicit power domain creation
and shifter/isolation insertion will not be needed any more:
• Level shifter, isolation cell, state retention cell, power switch cell definition.
• Level shifter, isolation cell, power switch cell insertion rule definition.
• Power/ground net creation.
• Power domain and power/ground net connection creation.
• Hard macro/IP low power intent modeling
• Library set creation.
• Different analysis view creation based on combination of different operating corner or power
mode creation and bind with different library set.
Based on different analysis views, you can practice MMMC clock tree insertion and design optimization
on different stages such as preCTS, postCTS, and postRoute stages, respectively.

Refer to the foundation flow document for detailed info. Here is a brief description about the low power
foundation flow and how to run the flow in this workshop.
The low power foundation flow consists of three flow setup/environment scripts and a number of the
implementation scripts.
Flow Setup/Environment Scripts
• setup.tcl: It is unique for each design. It specifies variables for the design (netlist), libraries,
constraints including CPF, and some timing views.
Implementation Scripts
• run_init.tcl: create initial Database

• run_place.tcl: Cell Placement and preCTS optimization
• run_cts.tcl: Clock Tree Synthesis and Optimization
• run_postcts_hold.tcl: PostCTS Hold Fixing
• run_route.tcl: Global/Detail Route
• run_postroute.tcl: PostRoute Optimization
• run_signoff.tcl: Signoff Timing/Verify
Each flow step has optional pre and post step plugins for user to customize this step. Each step script
will automatically source its plugin scripts.
Flow Directory Structure
The workshop is under LowPower directory. Under the LowPower, the directory structure is as follows:
• LIBS/: Contains the libraries including CapTable, LEF, lib

• INPUT/: The workshop data including netlist, sdc, and CPF
• PLUG/: LP Foundation Flow Plug in script
Innovus/: All the Innovus plug scripts are in this directory
• SCRIPTS/: LP Foundation Flow Makefile generation script, flow environment/setup scripts

Innovus/: All LP Foundation Flow scripts are in this directory
• <YourWorkingDir>/: It is created by user to run the foundation flow there.

DBS/: It is created by foundation flow script to store all the saved DBs at each
Implementation step
LOG/: It is created by foundation flow script to store all the log files at each
Implementation step
RPT/: It is created by foundation flow script to store report files at each Implementation
step
make/: It is created by foundation flow script to stamp which step has been run.

Lab 1-2 Setting Up the Workshop
1. Go to the workshop directory (LowPower)

2. mkdir <yourWorkingDir>
3. cd <yourWorkingDir>
4. cp ../SCRIPTS/setup.tcl .
5. cp ../SCRIPTS/Makefile .
6. generate Make file: tclsh ../SCRIPTS/gen_flow.tcl -m flat all; It generates Makefile for all
the implementation steps (not shown in this workshop). Makefile file is created after this and go
through it in other tab for better understanding.
7. make –f Makefile [all|singleTarget]
Target “all” will run all the implementation steps(not recommended). singleTarget will run the single
implementation step such as “init”, “place”, “cts”, “cts”, “postcts_hold”, “route” and “postroute”.
After each implementation step is run, you can restore this step DB and browse it with the interface.
Foundation Flow Step: run_init.tcl
The script is in ./FF/INNOVUS directory. It will source the plug-in post_init.tcl in PLUG/INNOVUS.
1. At the command prompt, enter this command string:
make –f ../SCRIPTS/Makefile init
or make init also works here since Makefile is created in your working directory.
2. It will run run_init.tcl. The script loads the design; do the floorplan, power switch insertion,
power planning and routing; and then saves the init.enc DB in the ./DBS under your working
directory.
The followings are some detailed descriptions about the major stages in the run_init.tcl.
CPF
The completed CPF file../INPUT/rc.pfi_dac.cpf contains:

Technology
• Level shifter, isolation cell, state retention cell, power switch cell definition.
Design
• Library set creation.

• Power/ground net creation.

• Power domain and its power/ground net definition; the instances PG connection is done
automatically.
• Different analysis view creation.

• Level shifter, isolation cell, power switch cell, and state retention cell insertion rule definitions
In the run_init.tcl file two PLUGINS are called : pre_init.tcl and post_init.tcl. location: (
PLUGS/INNOVUS/)
Go through these files for better understanding.

Rapid Adoption Kit – Innovus Low-Power Design Flow
Lab 1-3 MMMC
EDI11 onwards only MMMC flow is supported. In the low power flow, users can either define the
MMMC using CPF commands or Innovus CTE commands (viewDefinition.tcl) or both. The
viewDefinitoin.tcl has higher priority.
In the LP foundation flow, users must specify the MMMC objects in setup.tcl, it then converts those
variables to viewDefinition.tcl under FF dir in your working directory for the design import. But, this
viewDefinition.tcl is not complete for power domain binding.
The power domain binding is through CTE command: update_delay_corner –power_domain.
a) In this workshop, this is done by read_power_intent -cpf/commit_power_intent (MMMC is defined
in CPF). Please check viewDefinition.tcl in the init.enc.dat under DBS directory.
b) If using foundation Flow association of delay corner and power domain can be specified in setup.tcl
set vars(dc,power_domains) List of power domains
c) viewDefinition.tcl can have explicitly have these commands
Loading and Committing CPF to the Innovus System
1. To load the CPF file into Innovus, use the read_power_intent -cpf command. To commit the
CPF in the Innovus, use the commit_power_intent command. Both commands are in run_init.tcl
and are executed automatically once you specify the CPF file through vars(cpf_file) in setup.tcl.
2. commit_power_intent also created implicit ISO or LS rules based on the power modes defined
in CPF. The implicit rules are background rules without “-pins” and are created between all
possible two domains even if there is no logic connection. Those implict rules are used by
optDesign/BTS/verifyPowerDomain commands to prevent or check any LP Errors.
3. After read_power_intent -cpf and commit_power_intent, run_init.tcl creates RC corners and
binds them to the views defined in CPF through the delay corners. The rc corners are specified
in the vars(rc_corners) and the binding is defined in the vars(delay_corner,rc_corner) in setup.tcl.
The delay corners are created by commit_power_intent. The delay corner name is the view name
followed by _dc such as <viewname>_dc.
run_init.tcl sets the active views for implementation based on the vars(active_setup_views) and
vars(active_hold_views) defined in setup.tcl. The first view in the view list is the default view.
MMMC scenario has been created by read_power_intent -cpf/commit_power_intent and some
Innovus CTE commands such as create_rc_corner and setup_analysis_view. You can take the
following steps to browse the created analysis views, delay corners, constraint modes, library
sets, RC corners and the relationship among them:
4. Restore DBS/init.enc by entering
innovus –init DBS/init.enc.
5. Choose Timing –MMMC Browser…

Rapid Adoption Kit – Innovus Low-Power Design Flow
You see a form with Analysis View List on the left side and Delay Corner List on the right side as shown
here.
You can click the + to browse the MMMC information.
New option wizard help is present as seen in the image below.
6. Click Close after you have browsed the MMMC.

Lab 1-4 Floorplan, Power-Switch Insertion and PPPR
The script ../PLUG/INNOVUS/post_init.tcl will be called automatically by run_init.tcl, In this script, it

will do floorplanning, power switch insertion, power planning and power routing steps.
Defining Power Domain Physical Attributes
Besides read_power_intent -cpf and commit_power_intent, for physical-related attributes such as

minGap and rsExts are needed to be specified for the power domains. Those attributes are defined by
Innovus command modifyPowerDomainAttr in the ../PLUG/INNOVUS/post_init.tcl which is
automatically run by run_init.tcl.
• MinGap is a halo around the domain fence, and serves as a placement blockage. The row will
cut in MinGap so that there is no row overlap between domains.
• RouteSearchExt is a search distance for the power router to look for a legal target to connect
the power net.
modifyPowerDomainAttr PD1 -minGaps 5.0 5.0 30.0 5.0

modifyPowerDomainAttr PD1 -rsExts 20.0 20.0 45.0 20.0

Floorplanning
The post-init plug-in ./PLUG/INNOVUS/post_init.tcl defines the die/core size using Innovus command
floorplan.

Power Domain Floorplan
The power domains need to be resized and reshaped after they have been placed in the core area. To
place, resize and reshape the power domain in the core area, use the Innovus command setObjFPlanBox
for rectangular power domain or setObjFPlanBoxList for rectilinear power domain. The power domain
floorplan is in ../PLUG/INNOVUS/post_init.tcl .
Power Switch Insertion
There are two types of the power switches: column and ring switches. This workshop uses the column-
type power switches. Those switches are inserted in the switchable domains after power domain
floorplan by addPowerSwitch.

Power Planning
Examine the../PLUG/INNOVUS/post_init.tcl script.

In this workshop, a power and ground ring is created for each power domain. An M8 stripe over the
PDmac1 and PDmac2 power domains is created to connect the column-type power switch cell. In the
addStripe command, combining option -over_power_domain 1, -over_pin 1 and -master HSWX1 to
generate and connect the stripe based on the pattern of power switch cell HSWXl in both PDmacl and
PDmac2 power domains.

Power Routing
The ../PLUG/INNOVUS/post_init.tcl connects power pins for blocks and standard cells in each power
domain as shown here.
Remember to close the Innovus session before starting the next lab.

Lab 1-5 Generating DB by run_init.tcl
After running the run_init.tcl script, the low power DB is created in DBS/init.enc. You can check
low power setup DB. Use reportShifter and reportIsolation to report shifter and isolation
connections.
1. Restore DBS/init.enc by entering
innovus -init DBS/init.enc
2. Type reportShifter -outfile LS_added_after_commit_power_intent.rpt in the command

line window and the level shifters that were added are reported in the
LS_added_after_commit_power_intent.rpt file.
3. Type reportIsolation -outfile ISO_added_after_commit_power_intent.rpt in the

command line window and the isolation cells that were added will be reported in the
ISO_added_after_commit_power_intent.rpt file.
How many isolation instances are reported?
4. Choose Power – Multiple Supply Voltage – Verify Power Domain
5. Select Shifter and Isolation Cell and remaining keep as it is.
6. Click OK to verify the power domains and.
7. Please find the answers in the command line window:

How many nets are missing required level-shifters?
How many nets are missing required isolation cells?
Note: Use verifyPowerDomain to check whether the power domains are correctly setup.
To apply this command independently, run
verifyPowerDomain –gconn –xNetPD –isoNetPD.

Module 2: Foundation Flow Step:

run_place.tcl

Lab 2-1 Creating a Domain-Aware Placement
1. The ./FF/INNOVUS/run_place.tcl does the domain aware placement and also preCTS
optimization. It has two plug-in scripts: pre_place.tcl and post_place.tcl under
../PLUG/INNOVUS.
2. The pre_place.tcl script is running before run_place.tcl. You can put setPlaceMode to
control place behavior such as controlling ISO/LS placement (no show in this workshop).
This script also sets modes such as setOptMode, setTrialRouteMode and always-on buffer
dontUse attributes for preCTS optimization. Command reportAlwaysOnBuffer is used to
check the always-on buffer availability. We will include more about preCTS optimization in
Lab 2-2.
3. The post_place.tcl script is executed after place_opt_design. It does tie-high/low insertion
and highlight ISO/LS for ISO/LS placement checking.
4. The run_place.tcl does the placement and pre-CTS optimization using the
place_opt_design Innovus command.
5. To run this foundation step, at the command prompt, enter the following:
make –f ../SCRIPTS/Makefile place
The placement result is shown here.


Lab 2-2 Optimizing the Domain-Aware preCTS
After place_opt_design finishes the placement part, this super-command do preCTS optimization.
An important part of domain-aware preCTS optimization is always-on buffering. It has big impact
on the optimization QoR.
Always-on Buffering
In designs that contain modules that are shut-off, there will be nets that need to be always-on
buffering. Here are some examples:
• Control signals of SRPG cells

• Enable nets of isolation cells
• Enable nets of power switch cells
• Feed-through nets
(These are nets crossing from one domain to another domain through shutoff power domain.)
Special buffers or always-on buffers are often used for buffering these nets, which have an extra
power pin that is connected to the different power net from primary power net of the location
domain.
More details about always-on buffers can be found at below link:
Always-on (AON) buffer insertion using Innovus system
Direct Link:
https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V000006D7LuUAK&pageN
ame=ArticleContent
The Innovus optDesign engine can automatically detect when always-on buffers are needed
according to the driver, receiver and location power domain; and insert the always-on buffers to
buffer the nets whenever necessary; and then define the global connection for the always-on buffers’
secondary power pins. Please run verifyPowerDomain –isoNetPD –xNetPD to check if there is any
lower power violation. It is also recommended to run CLP for signoff check.
In this workshop, you will need to buffer the always-on nets using always-on buffers. The
followings are the requirements for always-on buffering:
1. Always-on buffer needs to be defined in CPF using define_always_on_cell

2. Always-on buffer is not set to DontUse (using cmd setDontUse to set it false)
3. Always-on buffers should be bound to that power domain
4. Always-on buffer Site must be defined in that power domain
The pre_place.tcl sets the always-on buffers to don’t use and don’t touch to false and use
reportAlwaysOnBuffer to check the always-on availability as follows:
Always on buffers found for each power domain:
PowerDomain "PD09" (pd tag = "1") has 2 always on buffer(s) to use PowerDomain
"PDmac1" (pd tag = "2") has 2 always on buffer(s) to use PowerDomain "PDmac2"
(pd tag = "3") has 2 always on buffer(s) to use PowerDomain "PDcore" (pd tag =
"4") has 2 always on buffer(s) to use
Once always-on buffer is available, place_opt_design is able to use them whenever the always-on
buffers are necessary during DRV fixing. In this workshop, the PBUFX2 and PINVX1 is an always-
on buffer/inverter with a secondary power pin.
After completing the place_opt_design, you can find the initial timing summary and the preCTS
optimization final summary in the optDesign log in ./LOG/place.log.
What is the initial worse negative slack?
What is the worst max_tran violation?
What is the prects final worse negative slack?
What is the prect final worst max_tran violation?
DB Generated by run_place.tcl
After running run_place.tcl, the placed DB is created in DBS/place.enc. You can restore it using
the restoreDesign Innovus command and checking the placed and optimized result such as
shifter/isolation placement and running CLP. If there are still a number of DRVs, you can analyze
this DB and may run bufferTreeSynthesis to buffers the remaining DRV nets.


run_cts.tcl

Lab 3-1 Secondary Power Pin Routing
The ../PLUG/INNOVUS/pre_cts.tcl do the 2nd power pin routing and defines the clock buffers used by
ccopt. The clock specification is automatically generated by ccopt in ./FF/INNOVUS/run_cts.tcl. Both
regular buffers and always-on buffers may be used during ccopt, the engine is able to choose which
buffer it need during clock synthesis. If it uses always-on buffers, it can automatically connect the always-
on buffer’s 2nd power pin.
The pre_cts.tcl script is run before the cts step. It routes the secondary power pin for always-on buffers,
level shifters, and SRPG cells using the routePGPinUseSignalRoute command.
a) setPGPinUseSignalRoute PBUFX2:ExtVDD…
This command sets which secondary PG pin of a cell needs to be routed with signal routing.
PBUFX2 is the cell name and ExtVDD is the pin name. It needs to be consistent with the lib/lef
of this cell. Wildcard is supported, i.e. PBUF*:ExtVDD.
b) setNanoRouteMode –routeStripeLayerRange “4:8” to control the 2nd power pin routing layers.
c) routePGPinUseSignalRoute do the actual PG routing for the pins mentioned above.
The secondary PG routing result is shown below:

More information about secondary PG connection can be found at below link:

Title: Secondary power routing with NanoRoute and low power debugging tips
Direct Link:
https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000uU9jEAE&pageName=A
rticleContent

Lab 3-2 Running the Domain-Aware Clock Tree Synthesis
The ./FF/INNOVUS/run_cts.tcl synthesizes the clock trees. To run this foundation step, at the command
prompt, type the following:
make –f ../SCRIPTS/Makefile cts
DB Generated by cts step
After running the cts step, the CTS DB is created in DBS/cts.enc. You can restore it with the
restoreDesign and check the clock tree synthesized result, such as browsing the clock tree and viewing
the clock tree graphically.
Browsing the Clock Tree
1. Restore DBS/cts.enc by entering
innovus –init DBS/cts.enc.
2. To view the clock tree that crosses the power domains, choose Clock –CCopt Clock Tree
Debugger.
3. With defaults selected, in the CTD Configuration window, click OK.
4. Clock Tree Debugger for av_max3 corner is opened. Click on Visibility and control (on
the right top side).
5. Under visibility section -> select the PDMac2,PDcore . You can see the clock trees of these
two domains.

6 Expand the Clock trees by clicking the + next to Clock tree in the Control pane.
You can change the color of the clock tree in the debugger window by changing the color
in the pane that is associated with the tree
8. Click View -> Clock path browser Analysis views will pop up.
9. Select a skew group in the Browser pane.
10. Highlight the path by right-clicking on the selected path selecting Highlight – Max
Path and select the highlight color.
11. Notice that the path is highlighted in the debugger window.
12. Notice that the same path is also highlighted in the Innovus design window.
13. Before closing clear the highlight path and close.


run_postcts_hold.tcl

Lab 4-1 Running the Domain-Aware PostClock-Tree Synthesis
The ./FF/INNOVUS/run_postcts_hold.tcl does the domain aware postCTS optimization. The

optimization setups are the same as those in preCTS optimization. Always-on buffers are available
whenever necessary. In this workshop, we skip the postCTS hold optimization.
1. To run this foundation step, at the command prompt, type the following:
make –f ../SCRIPTS/Makefile postcts_hold
DB Generated by run_postcts.tcl
After running the run_postcts_hold.tcl script, the postCTS optimized DB is created in DBS/postcts.enc.
1. You can restore it using the restoreDesign Innovus command.
restoreDesign DBS/postcts.enc


run_route.tcl

Lab 5-1 Routing the Design
The ./FF/INNOVUS/run_route.tcl routes the design. It uses plug-in script: pre_route.tcl under
../PLUG/INNOVUS.
1. To run this foundation step, at the command prompt, type the following:
make –f ../SCRIPTS/Makefile route
DB Generated by run_route.tcl
After running the run_route.tcl script, the routed DB is created in DBS/route.enc. You can restore it using
the restoreDesign Innovus command.
Next, explore GUI highlight and power debug using the routed DB.
Highlighting the Results
1. Restore DBS/route.enc by entering

innovus –init DBS/route.enc
2. Select Physical View above the All Colors button. Deselect the visibility for types Net and
Special Nets. This choice turns them off and allows better visibility of the analysis results.
3. Choose Power – Multiple Supply Voltages – Highlight Power Domain.

4. Try to select different objects and then click Highlight to see selected object highlighted in
the interface.

5. Deselect the objects and Clear All to clear the highlights and then try other objects.
6. Click the Signal Nets/HLS Cell tab, select the PDcore power domain for Src. of PD.
7. Click Add to add one entry to the left panel, and then select this new added entry Net:PDcore

8. Click Highlight to see nets inside PDcore to be highlighted in the interface. Deselect Net and
Special Net under All Colors.
Do you find any net routed as feed through?

9. Click Clear All to clear the highlights.

10. Click Close to close the form.


run_postroute.tcl

Lab 6-1 Running a Domain-Aware Postroute Optimization
The ./FF/INNOVUS/run_postroute.tcl does the domain-aware postroute optimization. After

optimization, you can find out the final timing numbers in the optDesign log in
./LOG/postroute.log.
What is the worst slack reported by optDesign?
1. To run this foundation step, at the command prompt, enter this command string:
make –f ../SCRIPTS/Makefile postroute
DB Generated by run_route.tcl
1. After running the run_postroute.tcl script, the postroute optimized DB is created in

DBS/postroute.enc. You can restore it using the restoreDesign Innovus command.
The optDesign Innovus command can do leakage power optimization while optimizing
timing and area by setting setOptMode -leakagePowerEffort.
Note: In this workshop, you do not turn on this option. If you want to turn it on, you need
to load the HVT, RVT, and LVT libraries.

Congratulations on finishing the Innovus Low-Power Design Flow CPF Implementation lab.
Workshop Summary
You completed the following steps to implement a multiple-power-domain design by CPF under
MMMC.
• Create Power Domain and Insert Level Shifter and Isolation Cell using CPF.
• MSV floorplanning
• MSV power gating
• MSV power planning and routing
• MMMC optimization and always-on buffering.
• Power mode aware clock tree synthesis
• 2nd power pin routing
We have used the Innovus LP foundation flow to go through each step. You can see the default
command/option setups throughout the flow by checking the Innovus run logs in the LOG
directory of your run directory.
Although the test case design is small, all steps that have been performed are applicable to a
design of a larger size.
Workshop Limitation
This workshop uses the general library developed by Cadence so that we can deliver the workshop
to customers. However, the library is still in the first release, it still needs some enhancements
such as the pin access for the route.


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Rapid Adoption Kit - Innovus Low-Power Design Flow

Cadence Design Systems, Inc.

Rapid Adoption Kit (RAK)

Innovus Low-Power Design Flow

Tool Version – Innovus Implementation System 18.10

COPYRIGHT © 2018, CADENCE DESIGN SYSTEMS, INC.

Module 1: Getting Started .................................................................................................................. 4

COPYRIGHT © 2018, CADENCE DESIGN SYSTEMS, INC.

Module 1: Getting Started

COPYRIGHT © 2018, CADENCE DESIGN SYSTEMS, INC.

Lab 1-1 Introduction to the Labs

Objective: To introduce the concepts and materials in the workshop.

Multiple Supply Voltages (MSV) and Power Shut Off (PSO)

COPYRIGHT © 2018, CADENCE DESIGN SYSTEMS, INC.

Flow Setup/Environment Scripts

• run_init.tcl: create initial Database

Flow Directory Structure

• LIBS/: Contains the libraries including CapTable, LEF, lib

• SCRIPTS/: LP Foundation Flow Makefile generation script, flow environment/setup scripts

• <YourWorkingDir>/: It is created by user to run the foundation flow there.

COPYRIGHT © 2017, CADENCE DESIGN SYSTEMS, INC.

Lab 1-2 Setting Up the Workshop

1. Go to the workshop directory (LowPower)

Foundation Flow Step: run_init.tcl

The completed CPF file../INPUT/rc.pfi_dac.cpf contains:

• Library set creation.

COPYRIGHT © 2017, CADENCE DESIGN SYSTEMS, INC.

• Different analysis view creation.

COPYRIGHT © 2017, CADENCE DESIGN SYSTEMS, INC.

Lab 1-3 MMMC

Loading and Committing CPF to the Innovus System

5. Choose Timing –MMMC Browser…

COPYRIGHT © 2017, CADENCE DESIGN SYSTEMS, INC.

6. Click Close after you have browsed the MMMC.

COPYRIGHT © 2017, CADENCE DESIGN SYSTEMS, INC.

Lab 1-4 Floorplan, Power-Switch Insertion and PPPR

The script ../PLUG/INNOVUS/post_init.tcl will be called automatically by run_init.tcl, In this script, it

Defining Power Domain Physical Attributes

Besides read_power_intent -cpf and commit_power_intent, for physical-related attributes such as

modifyPowerDomainAttr PD1 -minGaps 5.0 5.0 30.0 5.0

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Power Switch Insertion

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Examine the../PLUG/INNOVUS/post_init.tcl script.

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Lab 1-5 Generating DB by run_init.tcl

2. Type reportShifter -outfile LS_added_after_commit_power_intent.rpt in the command

3. Type reportIsolation -outfile ISO_added_after_commit_power_intent.rpt in the

How many isolation instances are reported?

4. Choose Power – Multiple Supply Voltage – Verify Power Domain

5. Select Shifter and Isolation Cell and remaining keep as it is.

6. Click OK to verify the power domains and.

7. Please find the answers in the command line window:

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Module 2: Foundation Flow Step:

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Lab 2-1 Creating a Domain-Aware Placement

The placement result is shown here.

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Lab 2-2 Optimizing the Domain-Aware preCTS