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Preliminary RT9108NB
15W Stereo Class-D Audio Power Amplifier

General Description Features
The RT9108NB is a 15W per channel, high efficiency z 8V to 26V Input Supply Range
Class D stereo audio amplifier for driving Bridge Tied Load z Ω Load, 10V Supply at 10% THD +N
6W/CH for an 8Ω
(BTL) speakers. The RT9108NB can drive stereo speakers z 15W/CH for an 8ΩΩ Load, 16V Supply at 10% THD +N
with load as low as 4Ω. Its high efficiency eliminates the z 90% Efficiency Eliminates Need for Heat Sinks
need for an extra heat sink when playing music. The gain z Four Selectable or Fixed Gain Settings
of the amplifier can be controlled by two gain select pins. z Mute Function Amplifier
The outputs are fully protected against shorts to GND, z Robust Pin - to- Pin Short Circuit Protection
PVCC, and output to output with an auto recovery feature z Thermal Protection with Auto Recovery Option
and monitored output. z Speaker Protection with Adjustable Power Limit
z Surface Mount TSSOP-28 (Exposed Pad) Package
The RT9108NB is available in a TSSOP-28 (Exposed Pad)
z RoHS Compliant and Halogen Free
package.
Applications
Ordering Information
z LCD-TV
RT9108NB
z Monitors
Package Type
CP : TSSOP-28 (Exposed Pad-Option 3) z DVD Players
Lead Plating System

G : Green (Halogen Free and Pb Free) Marking Information
Note : RT9108NBGCP : Product Number
RT9108NB YMDNN : Date Code
Richtek products are :
GCPYMDNN
` RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
` Suitable for use in SnPb or Pb-free soldering processes.
Simplified Application Circuit

RT9108NB
PVCC PVCCx BSPL FB
OUTPL
LINP PGND
OUTNL
GAIN0 GAIN0 BSNL FB
Audio
Source BSNR FB
GAIN1 GAIN1 OUTNR
PGND
OUTPR
RINP
BSPR FB
AGND
Copyright © 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
DS9108NB-P01T00 April 2013 www.richtek.com

1
RT9108NB Preliminary
Pin Configurations
(TOP VIEW)
SD 28 PVCCL
FAULT 2 27 NC
LINP 3 26 BSPL
LINN 4 25 OUTPL
GAIN0 5 24 PGND
GAIN1 6 23 OUTNL
AVCC 7
AGND
22 BSNL
AGND 8 21 BSNR
GVDD 9 20 OUTNR
PLIMIT 10 19 PGND
RINN 11 18 OUTPR
RINP 12 17 BSPR
NC 13
29
16 NC
MUTE 14 15 PVCCR
TSSOP-28 (Exposed Pad)
Functional Pin Description

Pin No. Pin Name Pin Function
Shutdown Logic Input for Audio Amp (High = outputs enabled). TTL logic levels
1 SD with compliance to AVCC.
Open Drain Output for Short Circuit Fault Status. Short circuit faults can be set to
2 FAULT auto recovery by connecting FAULT pin to SD pin.
3 LINP Positive Audio Input for Left Channel. Biased at 2.3V.
4 LINN Negative Audio Input for Left Channel. Biased at 2.3V.
5 GAIN0 Gain Select Least Significant Bit.
6 GAIN1 Gain Select Most Significant Bit.
7 AVCC Analog Supply Input.
8, Analog Ground. Connect to the thermal pad. The exposed pad must be soldered
AGND
29 (Exposed Pad) to a large PCB and connected to AGND for maximum power dissipation.
9 GVDD High Side FET Gate Drive Supply. Nominal voltage is 5V.
10 PLIMIT Power Limit Level Adjustment.
11 RINN Negative Audio Input for Right Channel. Biased at 2.3V.
12 RINP Positive Audio Input for Right Channel. Biased at 2.3V.
13, 16, 27 NC No Internal Connection.
14 MUTE Mute Logic Input for Audio Amp (Low = outputs enabled).
Power Supply Input for Right Channel H-Bridge. Right channel and left channel
15 PVCCR
power supply inputs are connected internally.
17 BSPR Bootstrap I/O for Right Channel, Positive High Side FET.
18 OUTPR Class-D H-Bridge Positive Output for Right Channel.
www.richtek.com DS9108NB-P01T00 April 2013

2
Pin No. Pin Name Pin Function
19, 24 PGND Power Ground for H-Bridges.
20 OUTNR Class-D H-Bridge Negative Output for Right Channel.
21 BSNR Bootstrap I/O for Right Channel, Negative High Side FET.
22 BSNL Bootstrap I/O for Left Channel, Negative High Side FET.
23 OUTNL Class-D H-Bridge Negative Output for Left Channel.
25 OUTPL Class-D H-Bridge Positive Output for Left Channel.
26 BSPL Bootstrap I/O for Left Channel, Positive High Side FET.
Power Supply Input for Left Channel H-Bridge. Right channel and left channel
28 PVCCL
power supply inputs are connected internally.

3
Function Block Diagram
PVCCL
SD VDDP
GVDD
FAULT BSNL
DRIVER OUTNL
BSPL
PLIMIT
DRIVER OUTPL
PGND
LINN
LINP Modulator PVCCR

VDDP
RINN BSNR
RINP DRIVER OUTNR
BSPR
MUTE
DRIVER OUTPR
GAIN
GAIN0
Control PGND
GAIN1
AVCC UVLO OVP OTP OCP

AGND
Operation
The RT9108NB is a 15W (per channel) efficient Class-D RT9108NB has protection from over current conditions
audio power amplifier for driving bridged-tied stereo caused by a short circuit on the output stage. The short
speakers. The RT9108NB uses the three-level modulation circuit protection fault is reported at the FAULT pin as a
scheme (BD model) that allows operation without the low state. The amplifier outputs are switched to a Hi-Z
classic LC reconstruction filter when the amplifier drives state when the short circuit protection latch is engaged.
is driving an inductive load. The internal close-loop The latch can be cleared by cycling the SD pin through
modulator enables the negative error feedback, which the low state. If automatic recovery from the short circuit
improves the THD+N of output signal. protection latch is desired, connect the FAULT pin directly
An adjustable power limiter is included in the modulator to the SD pin. This allows the FAULT pin function to
to protect the load speaker. The adjustable power limiter automatically drive the SD pin low which clears the short-
allows the user to set a “virtual” voltage rail lower than circuit protection latch.
the chip supply to limit the amount of current through the The RT9108NB can drive stereo speakers as low as 4Ω.
speaker. The high efficiency of the RT9108NB, 90%, eliminates
the need for an external heat sink when playing music.

4
Absolute Maximum Ratings (Note 1)
z Supply Voltage, PVCCR, PVCCL, AVCC --------------------------------------------------------------- −0.3V to 30V
z Input Voltage, SD, GAIN0, GAIN1, FAULT ------------------------------------------------------------- −0.3V to (AVCC + 0.3V)
z Output Voltage, OUTPR, OUTPL, OUTNR, OUTNL ------------------------------------------------- −0.3V to (PVCCx + 0.3V)
z Bootstrap Voltage, BSPR, BSPL, BSNR, BSNL ---------------------------------------------------- −0.3V to (PVCCx + GVDD)
z Other Pins ------------------------------------------------------------------------------------------------------ −0.3V to (GVDD + 0.3V)
z Power Dissipation, PD @ TA = 25°C
TSSOP-28 (Exposed pad) ---------------------------------------------------------------------------------- 3.44W
z Package Thermal Resistance (Note 2)
TSSOP-28 (Exposed pad), θJA ---------------------------------------------------------------------------- 29°C/W
TSSOP-28 (Exposed pad), θJC --------------------------------------------------------------------------- 1.2°C/W
z Junction Temperature ---------------------------------------------------------------------------------------- 150°C
z Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------ 260°C
z Storage Temperature Range ------------------------------------------------------------------------------- −65°C to 150°C
z ESD Susceptibility (Note 3)
HBM (Human Body Model) --------------------------------------------------------------------------------- 2kV
MM (Machine Model) ---------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions (Note 4)

z Supply Voltage, PVCCR = PVCCL ---------------------------------------------------------------------- 8V to 26V
z Junction Temperature Range ------------------------------------------------------------------------------- −40°C to 125°C
z Ambient Temperature Range ------------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(PVCCx = 12V, RL = 8Ω, TA = 25°C, unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
SD, GAIN0, Logic-High VIH 3 -- -- V
GAIN1, MUTE
Input Voltage Logic-Low VIL -- -- 0.8 V
Low Level Output Voltage VOL FAULT, RPULL-UP = 100kΩ -- -- 0.8 V
High Level Input Current IIH SD, GAIN0, GAIN1, MUTE, VI = 3V, -- -- 50 μA
Low Level Input Current IIL SD, GAIN0, GAIN1, MUTE, VI = 0.8V, -- -- 10 μA
Class-D Output Offset Voltage
|VOS| VI = 0V, Gain = 36dB -- 10 25 mV
(measured differentially)
Quiescent Supply Current IQ VSD = 3V, no load -- 20 35 mA
Quiescent Supply Current in VSD = 0.8V, no load
IQ_SHDN -- -- 2 mA
Shutdown Mode
Drain-Source On-State High Side -- 250 --
RDS(ON) IO = 500mA, TJ = 25°C mΩ
Resistance Low Side -- 200 --
VGAIN0 = 0.8V 19 20 21
VGAIN1 = 0.8V
VGAIN0 = 3V 25 26 27
Gain G dB
VGAIN0 = 0.8V 31 32 33
VGAIN1 = 3V
VGAIN0 = 3V 35 36 37

5

Turn-On Time tON VSD = 3V -- 14 -- ms
Turn-Off Time tOFF VSD = 0.8V -- 1 -- ms
Gate Drive Supply VGVDD IGVDD = 2mA 4.5 5 5.5 V
Power Supply Ripple 200mVPP ripple at 1kHz, Gain = 20dB, − 70
PSRR -- -- dB
Rejection Inputs ac-coupled to AGND
Continuous Output Power PO THD + N = 10%, fIN = 1kHz, PVCC = 13V -- 10 -- W
Total Harmonic Distortion +
THD + N fIN = 1kHz, PO = 5W -- 0.1 -- %
Noise
20Hz to 22kHz, A-weighted filter, -- 100 -- μV
Output Integrated Noise VN
Gain = 20dB -- −80 -- dBV
Crosstalk VO = 1VRMS, Gain = 20dB, fIN = 1kHz -- −80 -- dB
Maximum output at THD + N < 1%,
Signal-to-Noise Ratio SNR fIN = 1kHz, Gain = 20dB, A-weighted -- 98 -- dB
filter
Oscillator Frequency fOSC 220 300 380 kHz
(PVCCx = 24V, RL = 8Ω, TA = 25°C, unless otherwise specified)

SD, GAIN0, Logic-High VIH 3 -- -- V
GAIN1, MUTE
Input Voltage Logic-Low VIL -- -- 0.8 V
Low Level Output Voltage VOL FAULT, RPULL-UP = 100kΩ -- -- 0.8 V
High Level Input Current IIH SD, GAIN0, GAIN1, MUTE, VI = 3V -- -- 50 μA
Low Level Input Current IIL SD, GAIN0, GAIN1, MUTE, VI = 0.8V -- -- 10 μA
Class-D Output Offset
Voltage (measured |VOS| VI = 0V, Gain = 36dB -- 15 30 mV
differentially)
Quiescent Supply Current IQ VSD = 3V, No Load -- 30 50 mA
Quiescent Supply Current in VSD = 0.8V, No Load
IQ_SHDN -- -- 2 mA
Shutdown Mode
VGAIN0 = 0.8V 19 20 21
VGAIN1 = 0.8V
VGAIN0 = 3V 25 26 27
Gain G dB
VGAIN0 = 0.8V 31 32 33
VGAIN1 = 3V
VGAIN0 = 3V 35 36 37
PVCC Over Voltage Lockout OVP -- 30 -- V
Turn-On Time tON VSD = 3V -- 14 -- ms
Turn-Off Time tOFF VSD = 0.8V -- 1 -- ms
Gate Drive Supply VGVDD IGVDD = 2mA 4.5 5 5.5 V
Power Supply Ripple 200mVPP ripple at 1kHz, Gain = 20dB,
PSRR -- −70 -- dB
Rejection Inputs ac-coupled to AGND

6
THD + N = 10%, fIN = 1kHz,
Continuous Output Power PO -- 15 -- W
PVCC = 16V
Total Harmonic Distortion + PVCC = 16V, fIN = 1kHz, PO = 7.5W
THD + N -- 0.1 -- %
Noise (half-power)
20Hz to 22kHz, A-weighted filter, -- 100 -- μV
Output Integrated Noise VN
Gain = 20dB -- −80 -- dBV
Crosstalk VO = 1VRMS, Gain = 20dB, fIN = 1kHz -- −80 -- dB
Maximum output at THD + N < 1%,
Signal-to-Noise Ratio SNR fIN = 1kHz, Gain = 20dB, A-weighted -- 98 -- dB
filter
Oscillator Frequency fOSC 220 300 380 kHz
Thermal Trip Point TSD -- 170 -- °C
Thermal Hysteresis ΔTSD -- 15 -- °C
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.

7
Typical Application Circuit

PVCC
RT9108NB PVCC
100k 28
1k PVCCL
SD 1
SD
2 100µF 0.1µF 1nF
FAULT
1µF
3 0.22µF
LINP 26
BSPL FB
1µF 25 1nF
4 OUTPL
LINN 24
PGND
23
5 OUTNL 1nF
GAIN0 GAIN0 22
BSNL FB
6 0.22µF
PVCC GAIN1 GAIN1
0.22µF
10 21
7 BSNR FB
AVCC 20
Audio OUTNR 1nF
Source 1µF 19
8, 29 (Exposed Pad) PGND
AGND
18
1µF OUTPR 1nF
9 17
GVDD BSPR FB
10k 0.22µF
1k 10
PLIMIT PVCC
1µF 15
PVCCR
1µF 100µF 0.1µF 1nF
11
RINN
1µF
12
RINP MUTE 14 MUTE
Figure 1. Typical Application Circuit
PVCC RT9108NB PVCC

28
PVCCL
100k 0.1µF 1nF
1k 100µF
SD 1
SD
1µF 2
FAULT
3 0.22µF 22µH
LINP 26
BSPL
1µF 25 0.47µF
4 OUTPL
LINN 24
PGND
23
5 OUTNL 22µH 0.47µF
GAIN0 GAIN0 22
BSNL
6 0.22µF
PVCC GAIN1 GAIN1
0.22µF 22µH
10 21
7 BSNR
AVCC 20
Audio 8, OUTNR 0.47µF
Source 1µF 19
29 (Exposed Pad) PGND
AGND
1µF 18 0.47µF
OUTPR 22µH
9 17
GVDD BSPR
10k 0.22µF
1k 10
PLIMIT PVCC
1µF 15
PVCCR
1µF 100µF 0.1µF 1nF
11
RINN
1µF
12
RINP MUTE 14 MUTE
Figure 2. Typical LC Output Filter

8
Typical Operating Characteristics
Efficiency vs. Output Power Efficiency vs. Output Power
100 100
90 90
80 80
70 70
Efficiency (%)
Efficiency (%)
60 60
50 50
40 40
30 30
20 20
PVCC = 12V, f = 1kHz, Gain = 20dB PVCC = 24V, f = 1kHz, Gain = 20dB
10 10 LC Filter = 22μH +0.47μF, ZL = 8Ω
LC Filter = 22μH +0.47μF, ZL = 8Ω
0 0
0 1 2 3 4 5 6 7 8 9 10 0 2 4 6 8 10 12 14 16 18 20
Output Power (W) Output Power (W)
THD+N vs. Output Power THD+N vs. Output Power

20 20
10 10
10
5 5
5
2 2
1 2
1
THD+N (%)
THD+N (%)
0.5 0.5
1
0.2 0.2
0.5
0.1 0.1
1kHz 0.2
0.05 0.05 1kHz
0.02 20Hz 0.1
0.02
0.01 0.01
0.05
20Hz 10kHz
0.005 10kHz 0.005
0.002 0.02
PVCC = 12V, RL = 8Ω, Gain = 20dB 0.002 PVCC = 24V, RL = 8Ω, Gain = 20dB
0.001 0.01
0.001
10m 20m 50m 200m 500m 1 2 5 10 20 10m 20m 50m 200m 500m 1 2 5 10 20 50
Output Power (W) Output Power (W)
THD+N vs. Frequency THD+N vs. Frequency

10 10
5 5
2 2
1 1
0.5 0.5
THD+N (%)
THD+N (%)
0.2 0.2
0.1 0.1
0.05 0.05
0.02 5W 0.02 10W
0.01 0.5W 0.01
5W
0.005 2.5W 0.005
0.002 1W
0.002
PVCC = 12V, RL = 8Ω, Gain = 20dB PVCC = 24V, RL = 8Ω, Gain = 20dB
0.001 0.001
20 50 100 200 500 1k 2k 5k 10k 20k 20 50 100 200 500 1k 2k 5k 10k 20k
Frequency (Hz) Frequency (Hz)

9
Application Information
Amplifier Gain Setting GVDD Supply

The gain of the RT9108NB amplifier can be set by two The GVDD is used to supply the Gate Drivers for the output
input terminals, GAIN0 and GAIN1, shown as Table 1. full bridge transistors. Connect a 1μF capacitor from this
The gain setting is realized by changing the taps on the pin to ground for good bypass. The typical GVDD output
input resistors and feedback resistors inside the amplifier. voltage is 5V.
This causes the input impedance (ZI) to be dependent on
the gain setting. The actual gain settings are controlled Short Circuit Protection and Automatic Recovery
by the ratios of the resistors, so the gain variation from The RT9108NB has protection from over current conditions
part-to-part is small. However, the input impedance from caused by a short circuit on the output stage. The short
part-to-part at the same gain may shift by ±20% due to circuit protection fault is reported on the FAULT pin as a
shifts in the actual resistance of the input resistors. low state. The amplifier outputs are switched to a Hi-Z
Table 1. Gain Setting state when the short circuit protection latch is engaged.
Amplifier Input Impedance The latch can be cleared by cycling the SD pin through
GAIN1 GAIN0 GAIN (dB) (kΩ) the low state.
Typ Typ
If automatic recovery from the short circuit protection latch
0 0 20 56
is desired, connect the FAULT pin directly to the SD pin.
0 1 26 28
This allows the FAULT pin function to automatically drive
1 0 32 14
the SD pin low which clears the short-circuit protection
1 1 36 8.75 latch.
SD Operation Thermal Protection

The RT9108NB employs a shutdown mode operation Thermal protection on the RT9108NB prevents damage to
designed to reduce supply current (ICC) to the absolute the device when the internal die temperature exceeds
minimum level for power saving. The SD input terminal 170°C. There is a ±15°C tolerance on this trip point from
should be held high (see specification table for trip point) device to device. Once the die temperature exceeds the
in normal operation. Pulling SD low causes the outputs thermal set point, the device enters into the shutdown
to mute and the amplifier to enter a low current state. state and the outputs are disabled. This is not a latched
Leaving SD floating will cause the amplifier operation to fault. The thermal fault is cleared once the temperature of
be unpredictable. Never leave SD pin unconnected! the die is reduced by 15°C. The device begins normal
For the best power-off pop performance, turn off the operation at this point with no external system interaction.
amplifier in the shutdown mode prior to removing the power Thermal protection faults are NOT reported on the FAULT
supply voltage. terminal.

10
Power Limit the maximum output power for a given maximum input
The voltage at pin 10 can used to limit the power to levels voltage and speaker impedance.
below that which is possible based on the supply rail. Add 2
ææ RL ö ö
a resistor divider from GVDD to ground to set the voltage çç ç ÷ x VP ÷÷
è RL + 2 x RS ø
at the PLIMIT pin. An external reference may also be POUT = è ø for unclipped power
2 x RL
used if tighter tolerance is required. Also add a 1uF capacitor
Where:
from pin 10 to ground.
RS is the total series resistance including RDS(on),
The PLIMIT circuit sets a limit on the output peak-to-peak and any resistance in the output filter.
voltage. The limiting is done by limiting the duty cycle to fixed
RL is the load resistance.
maximum value. This limit can be thought of as a " virtual" VP is the peak amplitude of the output possible
voltage rail which is lower than the supply connected to within the supply rail.
PVCC. This " virtual" rail is 5 times the voltage at the VP = 5 × PLIMIT voltage if PLIMIT < 5 × VP
PLIMIT pin. This output voltage can be used to calculate POUT (10%THD) = 1.25 × POUT (unclipped)
PLIMIT Typical Operation with RT9108NB

Output Voltage
Test Conditions () PLIMIT Voltage Output Power (W)
Amplitude (VP-P)
PVCC=24V, Vin=1Vrms, GVDD 36.3 (thermally limited) 46
RL=8Ω, Gain=26dB
PVCC=24V, Vin=1Vrms, 2.94 18.5 31.8
RL=8Ω, Gain=26dB
PVCC=24V, Vin=1Vrms, 2.34 12.3 25.5
RL=8Ω, Gain=26dB
PVCC=24V, Vin=1Vrms, 1.62 6.2 18.2
RL=8Ω, Gain=26dB
PVCC=24V, Vin=1Vrms, GVDD 11.6 29.6
RL=8Ω, Gain=20dB
PVCC=24V, Vin=1Vrms, 3.00 10.4 26.6
RL=8Ω, Gain=20dB
PVCC=24V, Vin=1Vrms, 1.86 5.2 17.3
RL=8Ω, Gain=20dB
PVCC=12V, Vin=1Vrms, GVDD 9.35 23.4
RL=8Ω, Gain=20dB
PVCC=12V, Vin=1Vrms, 1.76 5 16.4
RL=8Ω, Gain=20dB

11
Thermal Considerations Layout Considerations

For continuous operation, do not exceed absolute For the best performance of the RT9108NB, the below PCB
maximum junction temperature. The maximum power Layout guidelines must be strictly followed.
dissipation depends on the thermal resistance of the IC
` Place the decoupling capacitors as close as possible to
package, PCB layout, rate of surrounding airflow, and
the AVCC, PVCCL, PVCCR and GND pins. For achieving
difference between junction and ambient temperature. The
a good quality, consider adding a small, good
maximum power dissipation can be calculated by the
performance low ESR ceramic capacitor between 220pF
following formula :
and 1000pF and a larger mid-frequency capacitor
PD(MAX) = (TJ(MAX) − TA) / θJA between 0.1μF and 1μF to the PVCC pins of the chip.
where TJ(MAX) is the maximum junction temperature, TA is Do not trace out the NC pins (Pin13, 16 and Pin27) to
the ambient temperature, and θJA is the junction to ambient avoid the pin short issue.
thermal resistance. ` Keep the differential output traces as wide and short as
For recommended operating condition specifications, the possible.
maximum junction temperature is 125°C and TA is the ` The traces of (LINP & LINN, RINP & RINN) and (OUTPL
ambient temperature. The junction to ambient thermal & OUTNL, OUTPR & OUTNR) should be kept equal width
resistance, θJA, is layout dependent. For TSSOP-28 and length respectively.
(Exposed Pad) packages, the thermal resistance, θJA, is
` The thermal pad must be soldered to the PCB for proper
28°C/W on a standard JEDEC 51-3 single-layer thermal
thermal performance and optimal reliability. The
test board. The maximum power dissipation at TA = 25°C
dimensions of the thermal pad and thermal land should
can be calculated by the following formula :
be larger for application. The vias should connect to a
PD(MAX) = (125°C − 25°C) / (28°C/W) = 3.571W for
solid copper plane, either on an internal layer or on the
TSSOP-28 (Exposed Pad) package
bottom layer of the PCB.
The maximum power dissipation depends on the operating
ambient temperature for fixed T J (MAX) and thermal
resistance, θJA. The derating curve in Figure 3 allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
4.0
Single Layer PCB
Maximum Power Dissipation (W)1
3.6
3.2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0.0
0 25 50 75 100 125
Ambient Temperature (°C)
Figure 3. Derating Curve of Maximum Power Dissipation

12
GND The decoupling

capacitor (CS)
CS must be placed
SD 28 PVCCL as close to the
Do not
FAULT 2 27 NC CB trace out IC as possible
Audio LINP 3 26 BSPL
Input CIN
LINN 4 25 OUTPL FB
GAIN0 5 24 PGND GND
GAIN1 6 23 OUTNL FB
The decoupling PVCC CS AVCC 7 22 BSNL
capacitor (CS) AGND CB
AGND 8 21 BSNR
must be placed GND GVDD 9 20 OUTNR FB
as close to the CG
PLIMIT 10 19 PGND GND
IC as possible Audio RINN 11 18 OUTPR FB
CIN CB
Input RINP 12 17 BSPR
NC 13 16 NC Do not The decoupling
29 trace out
MUTE 14 15 PVCCR capacitor (CS)
CS must be placed
as close to the
GND IC as possible
Figure 4. PCB Layout Guide

13
Outline Dimension
Dimensions In Millimeters Dimensions In Inches

Symbol
Min Max Min Max
A 1.000 1.200 0.039 0.047
A1 0.000 0.150 0.000 0.006
A2 0.800 1.050 0.031 0.041
b 0.190 0.300 0.007 0.012
D 9.600 9.800 0.378 0.386
e 0.650 0.026
E 6.300 6.500 0.248 0.256
E1 4.300 4.500 0.169 0.177
L 0.450 0.750 0.018 0.030
U 4.410 5.510 0.174 0.217
Option 1
V 2.400 3.000 0.094 0.118
U 5.500 6.170 0.217 0.243
Option 2
V 1.600 2.210 0.063 0.087
U 5.800 6.200 0.228 0.244
Option 3
V 2.600 3.000 0.102 0.118
28-Lead TSSOP (Exposed Pad) Plastic Package
Richtek Technology Corporation

5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

14
Datasheet Revision History
Version Data Page No. Item Description
P00 2012/9/27 first edition
P01 2013/4/19 datasheet modify

15

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®

15W Stereo Class-D Audio Power Amplifier

Lead Plating System

Simplified Application Circuit

DS9108NB-P01T00 April 2013 www.richtek.com

TSSOP-28 (Exposed Pad)

Functional Pin Description

www.richtek.com DS9108NB-P01T00 April 2013

DS9108NB-P01T00 April 2013 www.richtek.com

Function Block Diagram

LINP Modulator PVCCR

RINP DRIVER OUTNR

AVCC UVLO OVP OTP OCP

www.richtek.com DS9108NB-P01T00 April 2013

Recommended Operating Conditions (Note 4)

DS9108NB-P01T00 April 2013 www.richtek.com

Parameter Symbol Test Conditions Min Typ Max Unit

(PVCCx = 24V, RL = 8Ω, TA = 25°C, unless otherwise specified)

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Typical Application Circuit

Figure 1. Typical Application Circuit

PVCC RT9108NB PVCC

Figure 2. Typical LC Output Filter

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THD+N vs. Output Power THD+N vs. Output Power

THD+N vs. Frequency THD+N vs. Frequency

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Amplifier Gain Setting GVDD Supply

SD Operation Thermal Protection

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PLIMIT Typical Operation with RT9108NB

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Thermal Considerations Layout Considerations

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GND The decoupling

Figure 4. PCB Layout Guide

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Dimensions In Millimeters Dimensions In Inches

28-Lead TSSOP (Exposed Pad) Plastic Package

Richtek Technology Corporation

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