Digital Electronic Circuits

Goutam Saha
Indian Institute of Technology Kharagpur

Multiplication and Division

Lecture 30
Concepts Covered:

 Binary Multiplication

 A Combinatorial Circuit for Binary Multiplication

 Binary Division

 A Combinatorial Circuit for Binary Division

Binary Multiplication
Multiplicand
Factors Multiplier
0x0=0 1101 -----------------
0x1=0 10 Product
(13)10
1x0=0 ---------- 1101
0000 (2)10
1x1=1 1011
1101 ------
(26)10 Carry 1111---------- (13)10
x y m ---------------- 1101 (11)10
11010
0 0 0 1101 ------
0000 (143)10
0 1 0 1101
1101
1 0 0 11 (13)10 -------------------
10001111
(3)10
1 1 1 Carry 11 ----------
1101 ------
1101 (39)10
m = x.y ----------------
100111
4-bit x 2-bit Multiplication

x3 y0 x2 y0 x1 y0 x0 y0
x3 x2 x1 x0
y1 y0 x3 y1 x2 y1 x1 y1 x0 y1
-------------------
x3y0 x2y0 x1y0 x0y0 0
x3y1 x2y1 x1y1 x0y1 F.A. F.A. F.A. H.A.
------------------------------------------------------
m5 m4 m3 m2 m1 m0
m5 m4 m3 m2 m1 m0
4-bit x 4-bit Multiplication x3x2x1x0 : 1101
Example:
x3 y0 x2 y0 x1 y0 x0 y0 y3y2y1y0 : 1011

x3 y1 x2 y1 x1 y1 x0 y1
01 11 10 01 1 1st row adder
0
10 00 00 10 1 2nd row adder
F.A. F.A. F.A. H.A.
x3 y2 x2 y2 x1 y2 x0 y2 01 11 00 01 1 3rd row adder

1 0 0 0 1
F.A. F.A. F.A. H.A.
x3 y3 x2 y3 x1 y3 x0 y3 Result: 10001111

F.A. F.A. F.A. H.A.

m7 m6 m5 m4 m3 m2 m1 m0
Binary Division 1001

(0)11 1101 1110101

1101
11 1011 D = (1110101)2 = (117)10
00 0011 d = (1101)2 = (13)10
Dividend Quotient 0000 q = (1001)2 = (9)10
101
r=0
11 0110
Divider
0000
Divisor Remainder 101
11 1101
1101
10
Dividend = Divisor x Quotient + Remainder D = (1011)2 = (11)10
d = (11)2 = (3)10
D=dxq+r q = (11)2 = (3)10
r = (10)2 = (2)10
Unit Cell for Divider Array
x y bin x y d bout

. 0 0 0 0 0
0 0 1 1 1
S Y
bout (x – y) Full bin 0 1 0 1 0 Unit
0 D0
Subtractor 0 1 1 0 0 Cell
1 D1
1 0 0 1 1
0 1 1 0 1 0 1 Y = S’.D0 + S.D1
. S
2-to-1
Multiplexer
1 1 0 0 0 2-to-1
Multiplexer
1 1 1 1 1

Unit Cell Full d = x y bin

Subtractor bout = x’.y + x’.bin + y.bin
A Divider Circuit Example:
11 11 10 01 D: 1110101
D6 d3 D5 d2 D4 d1 D3 d0 1 0 0 0 0 1 d: 1101
00 01 01 10 11
.
q3
0 0 1 1 0 1 1 0 q: 1001
r: 0000
00 01 11 10 01
d3 d2 d1 D2 d0
0 0 1 1 1 0 0 1
00 11 11 00 11
q.
0
2 1 0 0 0 0 0 0
d3 d2 d1 D1 d0
0 bout

q1 . 0

d3 d2 d1 D0 d0
0

Units with 0 as an input

to the subtractor can
q0 . 0

use half-subtractor.
r3 r2 r1 r0
References:
 Donald P. Leach, Albert P. Malvino, and Goutam Saha, Digital Principles &
Applications 8e, McGraw Hill
 Lloris Ruiz A., Castillo Morales E., Parrilla Roure L., García Ríos A. Number
Systems. In: Algebraic Circuits. Intelligent Systems Reference Library, vol 66. Springer,
Berlin, Heidelberg
Conclusion:
• Product from binary multiplication of two 1-bit number is
obtained from logical AND operation of the numbers.
• Binary multiplication of more than 1-bit numbers can be
obtained by getting partial products of and adding them
after appropriate shift.
• A combinatorial circuit based multiplier circuit using cell
array performs the shift within the arrangement.
• Binary division of numbers give two binary outputs:
quotient and remainder. It involves subtraction of divisor
after appropriate shift.
• A combinatorial circuit based divider circuit using cell
array performs the shift within the arrangement.
• The shift operation can be done by sequential logic circuit.
There are other approaches to perform binary
multiplication and division.