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Spartan - 6 Project Card: User Manual
Spartan - 6 Project Card: User Manual
User Manual
Version 1.0
CHAPTER – 1
INTRODUCTION
Figure-A shows the Spartan-6 Low Cost board block diagram, which includes the
following components and features:
CHAPTER 2
CLOCK SOURCE
Spartan-6 FPGA works in different clock frequencies. But in Spartan 6 Project card we use only
20MHz fixed Oscillator settings (On-Board Clock Fixed), we may change the clock frequency in
program by using clock divider procedure.
CHAPTER-3
The Spartan-6 Project Card has a slide power switch. Moving the power switch Up for
Power ON and down for power OFF (SW1).
The Spartan 6 Project Card has a push button switch (named as RESET) which can be
configured as input by assigning the corresponding FPGA pin location.
Name FPGA
Reset(SW2) P37
The SPARTAN-6 Project Card board has 8 push button switches. These 8 push buttons
switches are used for giving inputs externally from the user. SWITCH3, SWITCH4, SWITCH5,
SWITCH6 has one side connected to ground and the other side connected to a pin on the
Spartan- 6 device via a 4.7K current limiting resistor. The other end of this resistor is connected
to 3.3V supply.
The other 4 switches are connected as matrix push buttons. These are 2x2 matrix keys.
SWITCH 7, SWITCH 8, SWITCH 17, SWITCH 18 are pull up to 3.3V via 4.7K resistor.
The Spartan-6 Project Card board has eight individual surface-mount LEDs located
immediately right to the slide switches. The LEDs are labeled L4 throughL11 (left to right).
Each LED has one side connected to ground and the other side connected to a pin on the
Spartan- 6 device via a 270E current limiting resistor. To light an individual LED, drive the
associated FPGA control signal High.
FPGA Pin P126 P127 P131 P132 P133 P134 P137 P138
PROM led is presented near to the PROM switch, and it is noted as L2 in Spartan-6
FPGA Project Card. when the program is downloaded in to the Project Card, PROM led is in
OFF state. After the downloading of program, the PROM led will blink (ON). This LED
indication is helpful to you to know about the status of downloading of program in to the Project
Card.
CHAPTER-4
LCD DISPLAY
Once mastered, the LCD is a practical way to display a variety of information using
standard ASCII and custom characters. However, these displays are not fast. Scrolling the
display at half-second intervals tests the practical limit for clarity.
The character LCD is power by +5V. The FPGA I/O signals are powered by
3.3V.However; the LCD recognizes the FPGAs output levels as valid Low or High logic levels.
The LCD controller accepts 5V TTL signal levels and the 3.3V LVC MOS outputs provided by
the FPGA meet the 5V TTL voltage level requirements.
The 390ohm series resistors on the data lines prevent over stressing on the FPGA and
Strata Flash I/O pins when the character LCD drives a High logic value. The character LCD
drives the data lines when LCD R/W is High. Most applications treat the LCD as a write only
peripheral and never read from the display and hence in this trainer the R/W pin is grounded by
default.
There are 8 LCD data bits are used and they are represented form LCDD0 to LCDD7. To
select a register and chip for operation, Register Select (RS) and Chip Select (CS) signals are
used for this purpose, to display the character in the LCD. We are using 16 × 2 LCD display, you
have to enable the each line in the LCD display follow the below instructions. (Initialization)
1st line enable X “80”
2nd line enable X “C0”
Function set X “38”
To clear the display X “01”
Character blinking X “0F”
Entry mode set X “06”
CHAPTER-5
There are four seven segment display are placed in Spartan 6 Project Card. Each display
was selected by the select line connected to its corresponding FPGA pin. For that four BC558
(PNP) transistors are used to select individual display. The segment in display is connected to the
FPGA pin via 120 ohm resistor.
CHAPTER-6
20 PIN HEADER
There are two 20 pin headers are used for connecting boards externally and for many
applications. By using these connectors we can connect external peripherals into the FPGA kit.
CHAPTER-7
Spartan 6 project card has one RTC (Real Time Clock) IC DS1340 in its onboard. It’s a
2-wire 8pin RTC IC, uses a low-cost 32.768 kHz crystal, it tracks time using several internal
registers. The clock/calendar automatically adjusts for months with fewer than 31 days, including
corrections for leap years. Each pin function and FPGA connections is given below.
CHAPTER-8
ADC
Spartan 6 Project Card has one SPI-compatible, single channel Analog to Digital
Converter (ADC) by using AD121S101 IC. It is a single channel, 12 bit, low power, high speed,
and single power supply with 2.7V - 5.25V range, successive approximation, serial interface IC.
And it is a 6 pin IC.
In IC 1st pin (VA) is connected to +3.3V supply and bypassed with 0.1uF capacitor.
2nd pin (GND) is directly connected to ground.
3rd pin (Vin) is a analog input, it ranges from 0V to VA.
4th pin (SCLK) is a serial digital clock input to the ADC IC. This controls the conversion
and readout processes.
5th pin (SDATA) is a serial digital data output.
6th pin (CS bar) is a chip select pin. When it is low then only the ADC conversion process
will start.
There are 16 sclk cycles are required to complete the conversion processs. And two
modes of operations (hold mode, track mode) for single conversion process. The device will
move from hold mode track mode at the 13th rising edge of sclk. When in track mode the
minimum amount of voltage will flow on the LSB bits. This will given in the below timing
diagram.
CS is chip select, which initiates conversions on the ADC and frames the serial data
transfers. SCLK (serial clock) controls both the conversion process and the timing
of serial data. Basic operation of the ADC begins with CS going low, which initiates
a conversion process and data transfer. Subsequent rising and falling edges of
SCLK will be labeled with reference to the falling edge of CS; for example,
"the third falling edge of SCLK" shall refer to the third falling edge of SCLK after
CS goes low.
Spartan 6 Project Card has one SPI-compatible, single channel Digital to Analog
Converter (DAC) by using DAC121S101 IC. It is a single channel, 12 bit, low power, high
speed, and power supply with the range of 2.7V - 5.25V, serial interface IC. And it is a 6 pin IC.
Input shift register has sixteen bits. The first two bits are "don't cares" and are followed
by two bits that determine the mode of operation (normal mode or one of three power-down
modes). The contents of the serial input register are transferred to the DAC register on the
sixteenth falling edge of SCLK. Normally, the SYNC line is kept low for at least 16
falling edges of SCLK and the DAC is updated on the 16th SCLK falling edge.
However, if SYNC is brought high before the 16th falling edge, the shift register is reset
and the write sequence is invalid. The DAC register is not updated and there is no change
in the mode of operation or in the output voltage.
CHAPTER-9
BUZZER
5V small size 2 pin buzzer is placed in Spartan 6 Project Card. Its one pin is connected to
5V supply. And the other pin is connected to the collector end of the transistor (BC547). The
transistors base is connected to the FPGA pin via 220ohm resistor. This buzzer is used in many
applications, to indicate the final result is achieved by the beep sound.
FPGA CONNECTIONS
RELAY
5V small size 5 pin relay is used in Spartan 6 Project Card. The pins are NC (normally
closed), NO (normally opened), COM, C1, C2 (coil ends). C1 is connected to cathode of the
diode (IN4001) and also connected to 5V supply. C2 is connected to anode of the diode and also
connected to collector of transistor (SL100). And the base of the transistor is connected to FPGA
pin via 1K resistor, also connected to 5V supply via 10K resistor and connected to ground via
10K resistor. When current is passing to the coil it produces the magnetic field, because of this
the switch is closed depending upon the requirement (NC or NO). COM, NC, NO pins are
connected to the P7 connector. Thus we can use the relay output for the other application.
FPGA CONNECTIONS
CHAPTER-10
1. After installing Xilinx software, go to Start Menu Programs Xilinx ISE 12.1
ISE Design toolsProject Navigator (refer Figure-1).
Figure-1
Figure-2
Figure-3
Figure-4
Figure-5
4. A window given in Figure-6 will appear.
In the Device and Design flow for the project, select
Product category All
Family Spartan6
Device XC6SLX4
Package TQ144
Speed -2
Synthesis Tool XST (VHDL / Verilog)
Simulator ISE Simulator (VHDL / Verilog)
Preferred Language VHDL
Then click "Next" and "Finish" (refer Figure-6, 7).
Figure-6
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Figure-35
Figure – 36
Figure-37
Figure-38
Figure-39
Figure-40
Figure-41
Figure-42
Figure-43
Figure-44
19. To generate a PROM file double click Create PROM File in the impact window. Refer
figure 45. Then the new window will open. Refer figure 46. PROM reset (sw2) switch is used to
reset the PROM IC.
Figure-45
Figure-46
Figure-47
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