DCO Presentation 2 PDF

BSc IT
Digital and Computer Organization

Semester - III
Copyright@ Amity University

What Is A Computer?
Historically, a computer was a job title, not a piece of equipment!
Requirements of a computer:
Process data
Store data
Move data between the computer and the outside
world
Control the operation of the above

Computer History - Electronic Era (1940 )
Generation 1 (1945 - 1958) – ENIAC
Developed for calculating artillery firing tables

Designed by Mauchly & Echert of the University of Pennsylvania
Generally regarded as the first electronic computer BIG!

18,000 tubes
70,000 resistors
10,000 capacitors
6,000 switches
30 x 50 feet
140 kW of power
Decimal number system used
Programmed by manually setting switches

Computer History - Electronic Era
Generation 1 – IAS (Institute for Advanced Studies)
Von Neumann and Goldstine

Took idea of ENIAC and developed concept of storing
a program in the memory
This architecture came to be known as the “von

Neumann” architecture and has been the basis for
virtually every machine designed since then
Features
Data and instructions (programs) are stored in
a single read-write memory
Memory contents are addressable by location,
regardless of the content itself
Sequential execution

Generation 2 (1958 - 1964)
Technology change -- Transistors

High level languages
Floating point arithmetic
Generation 3 (1964 - 1974)
Introduction of integrated circuits

Semiconductor memory
Microprogramming
Multiprogramming

Generation 4 (1974 - present)
Large scale integration / VLSI

Single board computers
Generation 5 (? - ?)
VLSI / ULSI
Computer communications networks
Artificial intelligence
Massively parallel machines

Performance Trends
Processor
Logic capacity: increases about 30% per year
Clock rate: increases about 20% per year
Performance: increases about 50% per year
Memory
DRAM capacity: increases about 60% per year (4x every 3
years)
Performance: increases about 3.4% per year
Disk
Capacity: about 60% per year
Performance: increases about 3.4% per year
What impact does this have on future computer systems?

What impact does this have on design decisions?

Performance Trends
Supercomputers
Log of Performance
Mainframes
Minicomputers
Microprocessors
Year
1970 1975 1980 1985 1990 1995

Computer Architecture (or Organization)

Computer Organization
& Architecture
In computer science and computer engineering, computer
architecture or digital computer organization is the conceptual
design and fundamental operational structure of a computer system.
Computer architecture comprises at least three main subcategories:

1. Instruction set architecture, or ISA, is the abstract image of a
computing system that is seen by a machine language (or assembly
language) programmer, including the instruction set, word
size, memory address modes, processor registers, and address and
data formats.
1. Microarchitecture, also known as Computer organization is a lower

level, more concrete and detailed, description of the system that
involves how the constituent parts of the system are interconnected
and how they interoperate in order to implement the ISA.[2] The size
of a computer's cache for instance, is an organizational issue that
generally has nothing to do with the ISA.
Computer Organization & Architecture
System Design which includes all of the other hardware components within
a computing system such as:
1. System interconnects such as computer buses and switches
2. Memory controllers and hierarchies
3. CPU off-load mechanisms such as direct memory access (DMA)
4. Issues like multiprocessing.
The coordination of abstract levels of a processor under changing

forces, involving design, measurement and evaluation. It also includes
the overall fundamental working principle of the internal logical structure
of a computer system.

Layer View of Computer System

A SIMPLE COMPUTER ARCHITECTURE
PC CONTROL UNIT MAIN MEMORY
REGISTERS
+1
IR
CONTROL SIGNALS
MBR
LATCH
ALU CONTROL SIGNALS
BUS 1
BUS 3 MAR

BASIC COMPUTER ARCHITECTURE
REGISTER
• All modern CPU‟s have an array of registers

– usually at least 32 general purpose registers
– frequently some so-called gp registers have dedicated use
• Characteristics of registers
– usually contain one computer word
– can be accessed in one CPU cycle
• Functions of registers
– serve as source of operands
– serve as destination of results
– temporarily store intermediate results
– serve as index registers to access arrays
• Specialized registers
– floating point registers
– store constants ….frequently used values

• Other specialized registers
– program counter
– stack pointer
– frame pointer
– base register
– instruction register
– memory address register
– memory buffer register
– some systems use “general purpose” registers to perform some of these
functions
• Consequences of the use of registers

– faster program execution
– shorter instruction formats
– address mode flexibility

• The program counter (PC)

– stores address of next instruction to execute
– must be incremented after each instruction
– may be changed by function call or jump
– controls flow of program execution
• The instruction register contains the currently executing instruction

– holds instruction while it is being decoded
– opcode field provides input to control system indicating operation to
perform
– contains addresses of operands to be used in operation
– contains destination address of result
– contains information about addressing modes to be used

• The arithmetic/logic unit (ALU)
– performs arithmetic and logical functions
– add, subtract, multiply, divide, complement, shift…etc.
– function performed is determined by the control signals received
– will have input and output latches to hold operands and results
• The Memory Address Register (MAR)

– holds address of the location in memory to be accessed
– this may be the address of the next instruction to be fetched
– may be the address of an operand to be read from memory
– may be the address of information to be written to memory
• The Memory Buffer Register (MBR)

– holds values to be transferred between main memory and the CPU
– data or instructions read from memory
– values to be written to memory
– most modern machines are capable of transferring more than a single word

• Control Unit
– provides control signals necessary to control the hardware of the CPU
– may be hardwired
• signals are generated by a combinational logic circuit
• faster
• less flexible
• harder to design and debug
– may be microprogrammed
• signals are stored in control memory
• slower than hardwired
• more flexible
• easier to design and debug
– control signals are needed to control functions of various hardware units

and to direct the flow of information within the CPU

• Main Memory
– used to store programs and data
– Volatile
– usually uses DRAM…dynamic random access memory

• slower than static ram
• must be refreshed
• requires fewer transistors to implement
• improves packing density on IC…allowing larger, cheaper memories
– most memory is byte addressable

• retrieve a single byte per memory access
– can be organized to access a full word or even multiple words per access
– cache memory is a distinct memory positioned between the CPU and MM

• faster
• smaller
• more expensive
• CPU bus structure
– a bus is an “information path” connecting the various functional

units within the CPU
– generally will be capable of transmitting one entire word in

parallel
• will consist of one word length of “wires” or data paths
– the CPU will have multiple buses to improve the information

transfer options within the CPU to maximize the flexibility and
parallelism of the system

Four Levels of Computer Description
1. Global system structure
Overall system structure is defined
Major components identified
Processors
Control modules
Memory modules
Interconnection structure
Mostly a static description -- “black box” approach
2. Processor level
Architectural Features specified
Interfaces
Instruction sets
Data Representation
More detailed individual component specification

Four Levels of Computer Description
3. Register level
Specify internal operation of processor-level
components at the word level
Primitives:
Registers
Counters
Memories
ALUs
Clocks
Combinational logic
4. Gate level
Specify operations at the individual bit level
Gates are primitive elements
Very cumbersome to do manually (logic
minimization, etc.)

Interconnection Structures
Memory: Outputs data. Inputs
read, write, and timing signals,
addresses, and data.
I/O Module. Outputs data &

interrupt signals. Inputs control
signals, data, and addresses.
CPU: Outputs address, control

signals, and data. Inputs
instructions data, and interrupt
signals.
Bus Interconnection
Communication pathway connecting two or more devices.
Shared transmission medium - usually broadcast.
Typically 50 – 100s of separate lines divided into three
functional groups:
Data lines
• At this level „data‟ and „instruction‟ are synonymous.
• Width is a key determinant of performance.
(Example: 32 bit words, data bus 16 bits  2 cycles to transmit
one word).
Address lines
• Identify source or destination of data (ie address in memory)
• Width determines maximum memory capacity of system (ie 8080
has 16 bit address  64K address space). Control lines
Control lines
• Control and timing signals (read, write, ack, clock)
Bus Interconnection
– Parallel lines on circuit boards

– Ribbon cables
– Strip connectors on mother boards
– Sets of wires

Single Bus Problems
Lots of devices on one bus leads to:
Propagation delays
Long data paths mean that co-ordination of bus use can
adversely affect performance
If aggregate data transfer approaches bus capacity
Most modern systems have at least 4 busses to solve
this problem:
Processor bus
Cache bus
Dedicated bus for accessing system cache.
Local I/O bus
High speed I/O bus for connecting performance critical
peripherals such as high-speed networks, disk storage devices.
Standard I/O bus
Connects slower peripherals such as mouse & modems etc.
Traditional ISA (with Cache)

High Performance Architecture

Elements of Bus Design
Type
Dedicated vs. Multiplexed
Dedicated by functionality ie address vs. data or dedication to a
physical subset of components.
Arbitration Method
Only one module can have control of the bus at any one time.
Centralized vs. Distributed
Timing
Synchronous vs. Asynchronous
Bus Width
Address
Data
Data Transfer Type
Read, Write, Read-modify-write, Read-after-write, Block

Bus Arbitration
Hardware arbitration
Serial arbitration – daisy chain Bus Bus Bus Bus
Parallel arbitration arbiter 1 arbiter 2 arbiter 3 arbiter 4
Dynamic arbitration algorithms
System can change the priority
Bus Ready
of the devices during normal operation.
Time slice – fixed length time slice of Priority Encoder
bus time offered sequentially to each
processor in round robin fashion.
Polling – address of each device in
turn placed on polling lines. A device 2 X 4 Decoder
may activate bus busy if it is being
polled.
LRU – Least recently used.
FIFO – First in first out. Hardware for parallel arbitration
Rotating Daisy-chain – dynamic
extension of the daisy chain.

A Bus Organization of Seven CPU registers

Data Transfer Type
Bus supports various data transfer types
Write (Master to slave)
Read (Slave to master)
Multiplexed address/data bus

Write (Cycle 1 : Address, Cycle 2 : Data)
Read (Cycle 1 : Address, Delay, Cycle ?: Data)
Non-multiplexed address/data bus

Write (Address & Data both sent in same cycle).
Read (Address followed by data once address is stabilized)
Other types of transfer include:

Read after write
Block data transfer (Address + multiple blocks of data)

Memory System Overview
Memory systems can be classified according to the
following key characteristics:
Location
• External – Peripherals such as disk and tape etc.
• Internal – Main memory, Registers, Cache
Capacity
Unit of Transfer
Access Method
Performance
Physical Type (What it is made of)
Physical Characteristics (How it behaves)
Organization

Memory Characteristics (cont…)
Capacity
Expressed in bytes or words.
Typical word lengths are 8, 16, 32 bits
Unit of Transfer
For internal memory this is equal to the number of data lines
into and out of the memory module.
Word length or longer (ie 64, 128, or 256 bits)
Concepts of Size
• Word: Natural unit of organization within memory.
No. or bits to represent a number, Length of one instruction.
Many exceptions.
• Addressable Units:
Either word or byte.
Maximum addressable units = 2A (where A = no. of bits in the address)
• Unit of transfer
No. of bits read into and out of memory.
Addressable unit or larger (block)
Access Method
Sequential Access
Data organized into units called records.
Access is linear sequenced.
Shared read/write mechanism that is physically moved to
read/write data.
Access time – varied.
Example: Tape Unit.
Direct Access
Shared read/write mechanism
Individual records have a unique physical address / location.
Access by direct access to general vicinity + local sequential
searching.
Example: Disk Units.
Access Method
Random Access
Each addressable location in memory has a unique, physically
wired addressing mechanism.
Access time is independent of previous accesses.
Access time is constant.
Example: Main Memory + some Caches.
Associative:
Random access type of memory
Supports comparison of desired bit locations within a word for a
specified match on many words simultaneously
Word is retrieved based on a portion of its contents rather than
its address.
Constant retrieval time
Example: Many caches.
Performance
Access Time (latency)
Random Access = time taken to perform a read or write.
Non-random access memory = time to position read-write mechanism
at desired location.
Memory Cycle Time
Access time + additional time required before a second access can
commence.
Affected by behavior of the system bus not the processor.
Transfer Rate
Rate at which data can be transferred into or out of a memory unit.
For random access memory = 1/(cycle time).
Non random-access memory
TN = TA + ( N / R)
TN = Average time to read or write N bits
TA = Average access time
N = Number of bits
R = Transfer rate, in bits per second (bps)

Magnetic Disks
Tracks: Hard Disk platters arrange data
into concentric circles, rather than one
large spiral, as some other mediums use.
Each circle is called a Track.
Sectors: The smallest addressable unit
on a Track. Sectors are normally 512
bytes in size, and there can be hundreds
of sectors per track, depending on
location.
(Constant bit density – more sectors on
outer tracts)
Heads: The devices used to write and
read data on each platter.
Cylinders: Platters on a hard disk are
stacked up, and so are the http://www.pcguide.
heads. Concentric circles from each com/ref/hdd/geom/t
parallel platter form a cylinder. (Think racksDifference-
Stargate!) c.html

Reading and Writing
SEEK: Disk controller sends a command to move
the arm over the proper track. = Seek Time.
Seek time
Minimum / Maximum
Average? Sum of all possible seeks divided by the number of possible
seeks. What is wrong with this???
Rotation latency (delay)
Time for requested sector to rotate under the head.
Average = halfway around disk. (0.5)
If a disk rotates at 10,000 RPM
Avg Rotation time = 0.5 / 10,000 RPM
= 0.5 / (10,000/60) RPS
= 0.0030 sec = 3.0 ms.
Transfer time
Time it takes to transfer a block of bits. (typically a sector)
Function of block size, disk size, rotation speed, recording density, etc.

Example
What is the average time to read or write a 512-byte sector for a
disk? The advertised average seek time is 5ms, the transfer rate is
40MB/sec, it rotates at 10,000 RPM, and the controller overhead is
0.1ms. Assume the disk is idle so that there is no queueing delay. In
addition, calculate the time assuming the advertised seek time is
three times longer than the measured seek time.
Answer:
Average disk access = average seek time + average rotational delay
+ transfer time + controller overhead.
= 5ms + 0.5 + 0.5KB + 0.1ms

10,000 RPM 40 MB/sec
= 1.67ms + 3.0ms + 0.013ms + 0.1ms = 4.783ms

Memory Hierarchy
Trade-offs
Speed
Cost
Size

Technology Trends
• Processor
– logic capacity: about 30% per year
– clock rate: about 20% per year
• Memory
– DRAM capacity: about 60% per year (4x every 3 years)
– Memory speed: about 10% per year
– Cost per bit: improves about 25% per year
• Disk
– capacity: about 60% per year
– Total use of data: 100% per 9 months!
• Network Bandwidth
– Bandwidth increasing more than 100% per year!
Levels of Representation
High Level Language
Program
Compiler
Assembly Language
Program
Assembler
Machine Language
Program
Machine Interpretation
Control Signal
Specification
Execution Cycle
Instruction Obtain instruction from program storage
Fetch
Instruction Determine required actions and instruction size

Decode
Operand
Locate and obtain operand data
Fetch
Execute
Compute result value or status
Result
Store Deposit results in storage for later use
Next
Instruction Determine successor instruction
The Role of Performance

Performance Metrics
• Response Time
– Delay between start end end time of a task
• Throughput
– Numbers of tasks per given time
• New: Power/Energy
– Energy per task, power

Relating the Metrics
• Performance = 1/Execution Time
• CPU Execution Time = CPU clock cycles

for program x Clock cycle time
• CPU clock cycles = Instructions for a

program x Average clock cycles per
Instruction

Register set with common ALU
Control unit operates the CPU bus system. For example:
R1 R2 + R3
1. SELA is used to place R2 into bus A.
2. SELB is used to place R3 into bus B.
3. OPR selects the arithmetic addition.
4. SELD is used to transfer the result into R1.
The buses are implemented with multiplexers of 3-state gates. The

state of 14 binary selection inputs specifies a control word. The 14-
bit control word.

Contd…...

Arithmetic & Logic Operations
ALU provides arithmetic and logic operations. The function
table of the ALU (presented here) is listed in shown table:

Stack Organization
A stack is a computer science, which means that the last item put
on the stack Last In First Out (LIFO)of is the first item that can be
taken off, like a physical stack of plates.
A stack-based computer system is one that is based on the use of

stacks.
Stack can reside in a portion of a large memory unit or it can be

organized as a collection of a finite number of (fast) registers.

Stack Organization
Organization of 6-word register stack

Stack Organization
1. Push (performed if stack is not full i.e. if FULL = 0):
2. Pop (performed if stack is not empty i.e. if EMTY = 0):

Stack Organization
Stack can also be implemented with RAM attached to a CPU:
A portion of memory is assigned to a stack operation, a processor

register is used as a stack pointer. A portion of memory is partitioned
into three segments: program, data, and stack.
Most computer do not provide hardware for checking stack overflow

or underflow if registers are used to store the upper limit (e.g. 3000)
and the lower limit (e.g. 4000), then after push SP can be compared
against the upper limit register, and after pop against the lower limit
register.
The advantage of the memory stack is that CPU can refer it without
having to specify an address: the address in always in SP and
automatically updated during a push or pop instruction.

Computer Memory with Program,
Data and Stack Segments

Stack Application
Reverse Polish Notation
A stack is effective for evaluating arithmetic expressions.
Arithmetic operations are usually written in infix notation: each operator

resides between the operands,
e.g.: (A * B) + (C * D),
where * denotes multiplication: A * B and C * D has to be computed and
stored. after the two products, sum (A * B) + (C * D) is computed, there is no
straight forward way to determine the next operation that is performed.
Arithmetic expressions can be presented in prefix notation: operators are

placed before the operands. The postfix notation (reverse Polish notation
(RPN)) places the operator after the operand.
e.g.:
A + B , infix notation
+AB , prefix notation
AB+ , postfix notation (RPN)

Contd…
Reverse Polish notation (RPN) , also known as postfix notation, is
an arithmetic formula notation, derived from the Polish
notation introduced in 1920 by the Polish mathematician Jan
£ukasiewicz.
RPN was invented by Australian philosopher and computer

scientist Charles Hamblin in the mid-1950s, to enable zero-address
memory stores.
As a user interface for calculation the notation was first used

in Hewlett-Packard's desktop calculators from the late 1960s and
then in the HP-35 handheld scientific calculator launched in 1972.
Implementations of RPN are stack-based; that is, operands are

popped from a stack, and calculation results are pushed back onto
it.

Contd…
In RPN the operands precede the operator, thus dispensing with the
need for parentheses.
For example, the expression 3 * ( 4 + 7) would be written as 3 4 7 +

*, and done on an RPN calculator as "3", "Enter", "4", "Enter", "7",
"+", "*".
Alternatively, and more-compactly, it could also be re-ordered and

written as 4 7 + 3 *, and done on an RPN calculator as "4", "Enter",
"7", "+", "3", "*".
Although this concept may seem obscure at first, RPN has the
advantage of being extremely easy, and therefore fast, for a
computer to analyze.

Practical implications
1. Calculations proceed from left to right
2. There are no brackets or parentheses, as they are unnecessary.
3. Operands precede operator. They are removed as the operation is

evaluated.
4. When an operation is made, the result becomes an operand itself (for

later operators).
5. There is no hidden state. No need to wonder if you hit an operator or

not.
Example:
The calculation: ((1 + 2) * 4) + 3 can be written down like this in RPN:

12+4*3+

The expression is evaluated in the following way (the Stack is displayed after Operation
has taken place):
Input
Stack
Operation
1
1
Push operand
2
1, 2
Push operand
+
3
Addition
4
3, 4
Push operand
*
12
Multiplication
3
12, 3
Push operand
+
15
Addition
The final result, 15, lies on the top of the stack at the end of the calculation.
MICRO OPERATION
 In computer central processing units, micro-operations, also
known as a micro-ops or μ-ops, are detailed low-level instructions
used in some designs to implement complex machine instructions.
 Various forms of μ-ops have long been the basis for

traditional microcode routines used to simplify the implementation
of a particular CPU design or perhaps just the sequencing of certain
multi-step operations or addressing modes.
 Processors not only translate many machine instructions into a

series of μ-ops, but also do the opposite when appropriate; they
combine certain machine instruction sequences (such as a
compare followed by a conditional jump) into a more complex μ-op
which fits the execution model better and thus can be executed
faster or with less machine resources involved.

MICRO OPERATION
 The size of this cache may be stated in terms of how many

thousands of micro-operations it can store.
 Micro-operation can be categorized into many types as:
1. Register Transfer Micro-operation
2. Arithmetic Micro-operation
3. Logical Micro-operation
4. Shift Micro-operation

REGISTER TRANSFER
 Copying the contents of one register to another is a register transfer
 A register transfer is indicated as

R2  R1
 In this case the contents of register R2 are copied (loaded) into register
R1
 A simultaneous transfer of all bits from the source R1 to the
destination register R2, during one clock pulse
 Note that this is a non-destructive; i.e. the contents of R1 are not altered
by copying (loading) them to R2
 A register transfer such as
R3  R5
Implies that the digital system has
 the data lines from the source register (R5) to the destination register (R3)
 Parallel load in the destination register (R3)
 Control lines to perform the action
BASIC SYMBOLS FOR REGISTER TRANSFERS
Symbols Description Examples

Capital letters Denotes a register MAR, R2
& numerals
Parentheses () Denotes a part of a register R2(0-7), R2(L)
Arrow  Denotes transfer of information R2  R1
Colon : Denotes termination of control function P:
Comma , Separates two micro-operations A  B, B  A

BUS TRANSFER
Bus is a path(of a group of wires) over which information is transferred, from any
of several sources to any of several destinations.
From a register to bus: BUS  R
Register A Register B Register C Register D
Bus lines
Register A Register B Register C Register D

1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4
B1 C1 D 1 B2 C2 D 2 B3 C3 D 3 B4 C4 D 4
0 0 0 0
4 x1 4 x1 4 x1 4 x1
MUX MUX MUX MUX
x
select
y
4-line bus
BUS TRANSFER IN RTL
 Depending on whether the bus is to be
mentioned explicitly or not, register transfer
can be indicated as either
R2 R1
or
BUS R1, R2  BUS
 In the former case the bus is implicit, but in

the latter, it is explicitly indicated

MEMORY TRANSFER
 Collectively, the memory is viewed at the register level as a
device, M.
 Since it contains multiple locations, we must specify which
address in memory we will be using
 This is done by indexing memory references
 Memory is usually accessed in computer systems by putting

the desired address in a special register, the Memory Address
Register (MAR, or AR)
 When memory is accessed, the contents of the MAR get sent
to the memory unit‟s address lines
Memory Read
AR
unit Write
Data out Data in

MEMORY READ
 To read a value from a location in memory and load it into a

register, the register transfer language notation looks like this:
 This causes the following to occur

 The contents of the MAR get sent to the memory address
lines
 A Read (= 1) gets sent to the memory unit
 The contents of the specified address are put on the
memory‟s output data lines
 These get sent over the bus to be loaded into register R1

MEMORY WRITE
 To write a value from a register to a location in memory looks

like this in register transfer language:
 This causes the following to occur

 The contents of the MAR get sent to the memory address
lines
 A Write (= 1) gets sent to the memory unit
 The values in register R1 get sent over the bus to the data
input lines of the memory
 The values get loaded into the specified address in the
memory

ARITHMETIC MICROOPERATIONS
 The basic arithmetic microoperations are
 Addition
 Subtraction
 Increment
 Decrement
 The additional arithmetic microoperations are

 Add with carry
 Subtract with borrow
 Transfer/Load
 etc. …
Summary of Typical Arithmetic Micro-Operations
R3  R1 + R2 Contents of R1 plus R2 transferred to R3

R3  R1 - R2 Contents of R1 minus R2 transferred to R3
R2  R2’ Complement the contents of R2
R2  R2’+ 1 2's complement the contents of R2 (negate)
R3  R1 + R2’+ 1 subtraction
R1  R1 + 1 Increment
R1  R1 - 1 Decrement

LOGIC MICROOPERATIONS
 Specify binary operations on the strings of bits in registers
 Logic microoperations are bit-wise operations, i.e., they work on the
individual bits of data
 useful for bit manipulations on binary data
 useful for making logical decisions based on the bit value
 There are, in principle, 16 different logic functions that can be defined
over two binary input variables
A B F0 F1 F2 … F13 F14 F15
0 0 0 0 0 … 1 1 1
0 1 0 0 0 … 1 1 1
1 0 0 0 1 … 0 1 1
1 1 0 1 0 … 1 0 1
 However, most systems only implement four of these

 AND (), OR (), XOR (), Complement/NOT
 The others can be created from combination of these

LIST OF LOGIC MICROOPERATIONS
• List of Logic Microoperations
- 16 different logic operations with 2 binary vars.
- n binary vars → functions
• Truth tables for 16 functions of 2 variables and the

corresponding 16 logic micro-operations
x 0011 Boolean Function Name
Micro-Operations
y 0101
0000 F0 = 0 F0 Clear
0001 F1 = xy FAB AND
0010 F2 = xy' F  A  B’
0011 F3 = x FA Transfer A
0100 F4 = x'y F  A’ B
0101 F5 = y FB Transfer B
0110 F6 = x  y FAB Exclusive-OR
0111 F7 = x + y FAB OR
1000 F8 = (x + y)' F  A  B)’ NOR
1001 F9 = (x  y)' F  (A  B)’ Exclusive-NOR
1010 F10 = y' F  B’ Complement B
1011 F11 = x + y' FAB
1100 F12 = x' F  A’ Complement A
1101 F13 = x' + y F  A’ B
1110 F14 = (xy)' F  (A  B)’ NAND
1111 F15 = 1 F  all 1's Set to all 1's

SHIFT MICROOPERATIONS
 There are three types of shifts
 Logical shift
 Circular shift
 Arithmetic shift
 What differentiates them is the information that goes into the serial
input
• A right shift operation
Serial
input
• A left shift operation

Serial
input

ARITHMETIC SHIFT
In computer programming, an arithmetic shift is a shift operator, sometimes
known as a signed shift (though it is not restricted to signed operands). For
binary numbers it is a bitwis operationthat shifts all of the bits of its operand;
every bit in the operand is simply moved a given number of bit positions, and
the vacant bit-positions are filled in. Instead of being filled with all 0s, as in
logical shift, when shifting to the right, the leftmost bit (usually the sign bit in
signed integer representations) is replicated to fill in all the vacant positions
(this is a kind of sign extension).
A left arithmetic shift of a binary number by 1. The empty

position in the least significant bit is filled with a zero. (Note A right arithmetic shift of a binary
that arithmetic left shift may cause an overflow - in this way it number by 1. The empty position in
differs from logical left shift.) Note that the operation depicted the most significant bit is filled with a
is the same as that of the left logical shift. copy of the original MSB.

ARITHMETIC LOGIC SHIFT
S3
S2 Ci
S
1
S0
Arithmetic
Circuit
Select
0 4x1
Ci+1 1 F
2
MUX
i
3
E
i
Logic
Bi Circuit
Ai
Ai-1 shr
Ai+1 shl
S3 S2 S1 S0 Cin Operation Function

0 0 0 0 0 F=A Transfer A
0 0 0 0 1 F=A+1 Increment A
0 0 0 1 0 F=A+B Addition
0 0 0 1 1 F=A+B+1 Add with carry
0 0 1 0 0 F = A + B’ Subtract with borrow
0 0 1 0 1 F = A + B’+ 1 Subtraction
0 0 1 1 0 F=A-1 Decrement A
0 0 1 1 1 F=A TransferA
0 1 0 0 X F=AB AND
0 1 0 1 X F = A B OR
0 1 1 0 X F=AB XOR
0 1 1 1 X F = A’ Complement A
1 0 X X X F = shr A Shift right A into F
1 1 X X X F = shl A Shift left A into F

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BSc IT

Digital and Computer Organization

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Historically, a computer was a job title, not a piece of equipment!

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Developed for calculating artillery firing tables

Generally regarded as the first electronic computer BIG!

Decimal number system used

Programmed by manually setting switches

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Von Neumann and Goldstine

This architecture came to be known as the “von

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Technology change -- Transistors

Generation 3 (1964 - 1974)

Introduction of integrated circuits

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Large scale integration / VLSI

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What impact does this have on future computer systems?

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Computer architecture comprises at least three main subcategories:

1. Microarchitecture, also known as Computer organization is a lower

1. System interconnects such as computer buses and switches

2. Memory controllers and hierarchies

3. CPU off-load mechanisms such as direct memory access (DMA)

4. Issues like multiprocessing.

The coordination of abstract levels of a processor under changing

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ALU CONTROL SIGNALS

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• All modern CPU‟s have an array of registers

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• Consequences of the use of registers

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• The program counter (PC)

• The instruction register contains the currently executing instruction

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• The Memory Address Register (MAR)

• The Memory Buffer Register (MBR)

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– control signals are needed to control functions of various hardware units

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– used to store programs and data

– usually uses DRAM…dynamic random access memory

– most memory is byte addressable

– cache memory is a distinct memory positioned between the CPU and MM

– a bus is an “information path” connecting the various functional

– generally will be capable of transmitting one entire word in

– the CPU will have multiple buses to improve the information

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I/O Module. Outputs data &

CPU: Outputs address, control

– Parallel lines on circuit boards

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