UBIQUITOUS LAB ASSISTANT SYSTEM

ABSTRACT

CMOS SRAM cell is very less power consuming and have less read and write time. Higher cell
ratios can decrease the read and write time and improve stability. PMOS transistor with less
width reduces the power consumption. It has been noticed often that increased memory capacity
increases the bit-line parasitic capacitance which in turn slows down voltage sensing and make
bit-line voltage swings energy expensive. This result in slower and more energy hungry
memories. A technique of global bit line is used for reducing the power consumption and
increasing the memory capacity. SRAM is the most crucial part of memory designs and are
imperative in many simple or compound applications that implicate system on chip (SoCs).
Power dissipation and stability has now become the most essential area of concern in sub-
micron SRAM cell design with continuous technology scaling according to Moore’s law. At
latest, retrenchment of channel length MOSFET is directly proportional to the new technologies
generating step by step with new innovative tools. With an improvement in technology there is
a sudden retrenchment of channel length of MOSFET. Moreover, in this network of stability
SRAM has become very essential and major area to research in. Static noise margin generate
its crucial role in the stability of SRAM. The out performs of this SRAM cell in elaboration
with transient response and static noise margin.

CONTENTS

Abstract

Acknowledgement Pg.No.

Chapter 1: Introduction
1.1 Introduction 6
1.2 Types of SRAM 6
1.3 Difference between SRAM & DRAM 7

Chapter 2: Literature survey 8

Chapter 3: Methodology and Implementation

3.1 Circuit diagram 9
3.2 Component description 11
3.3 Circuit Design 13
3.4 Circuit description 14

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Chapter 4: Results and Discussion 16
Chapter 5: Conclusion and Future Work

5.1 Conclusion 18
5.2 Future Work 18
REFERENCES 19
APPENDIX 20

LIST OF FIGURES

Figure 1. -Circuit diagram-9

Figure 2. -Results-16

Figure 3. -Datasheet-20

Figure 4. –Photos captured during execution-21

LIST OF TABLES

Table 1: SRAM v/s DRAM -7

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CHAPTER 1: INTRODUCTION
1.1 Introduction
Static random-access memory (static RAM or SRAM) is a type of semiconductor memory
that uses bistable latching circuitry (flip-flop) to store each bit. SRAM exhibits data
remanence, but it is still volatile in the conventional sense that data are eventually lost when the
memory is not powered.The term static differentiates SRAM from DRAM (dynamic random
access memory) which must be periodically refreshed. SRAM is faster and more expensive than
DRAM; it is typically used for CPU cache while DRAM is used for a computer's main memory.
6T SRAM cell which consists of two crossly coupled inverters and access transistors to read
and write the data. In case of the SRAM cell the memory built is being stored around the two
cross coupled inverters. If we consider that, the input to the first inverter is logic 1 then the
output of this inverter will be logic 0. So, after one cycle the output of second inverter will be
logic 1. From this we can say that as long as the power is supplied to the SRAM cell logic 1
will be circulated in the inverters. Hence there is no need for periodic refreshing of the circuit.
Where as in DRAM the circuit need to be refreshed periodically. SRAM technology is most
preferable because of its speed and robustness. Therefore, SRAM is much faster when compared
with the DRAM

1.2 Types of SRAM:

Non-volatile SRAM:
Non-volatile SRAM have standard SRAM functionality, but they save the data when the power
supply is lost, ensuring preservation of critical information. nvSRAMs are used in a wide range
of situations such as networking, aerospace, and medical, among many others where the
preservation of data is critical and where batteries are impractical.
Pseudo SRAM:
PSRAMs have a DRAM storage core, combined with a self refresh circuit .They appear
externally as a slower SRAM. They have a density/cost advantage over true SRAM, without
the access complexity of DRAM.
By transistor type:
1. Bipolar junction transistor (used in TTL and ECL) – very fast but consumes a lot of
power
2. MOSFET (used in CMOS) – low power and very common today
3. By function:

1. Asynchronous – independent of clock frequency; data in and data out are controlled by
address transition
2. Synchronous – all timings are initiated by the clock edge(s). Address, data in and other
control signals are associated with the clock signals

The symmetric structure of SRAMs also allows for differential signaling, which makes small
voltage swings more easily detectable. Another difference with DRAM that contributes to
making SRAM faster is that commercial chips accept all address bits at a time. By comparison,
commodity DRAMs have the address multiplexed in two halves, i.e. higher bits followed by
lower bits, over the same package pins in order to keep their size and cost down.

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1.3 SRAM vs DRAM:

BASIC FOR COMPARISON SRAM DRAM

Speed Faster Slower

Size Small Large

Cost Expensive Cheap

Used in Cache memory Main memory

Density Less dense Highly dense

Construction Complex and uses Simple and uses capacitors and very

transistors and latches. few transistors.

Single block of memory 6 transistors Only one transistor.

requires

Charge leakage property Not present Present hence require power refresh

circuitry

Power consumption Low High

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CHAPTER-2

2.Literature survey

Here various attempts made by investigators to reduce the power dissipation in SRAM or to
develop low power and energy efficient SRAM. These investigations cover SRAMs operated
at low voltages reducing power dissipation, SRAMs using techniques like power gating in
which the circuits are switched off when they are not needed , SRAMs (drowsy) where the
power supply voltage is reduced to a lower value during standby mode and SRAMs based on
adiabatic techniques. Lowering the power supply voltage reduces the dynamic power quadratic
ally and leakage power exponentially. But power supply voltage scaling also limits signal swing
and thus reduces noise margin. Further, aggressive technology scaling in the sub-100nm region
increases the sensitivity of the circuit parameters to process variation (PV).Leakage currents are
mainly due to gate leakage current and sub threshold leakage current. High K gate technology
decreases the gate leakage current. Forward body biasing methods and dual Vt techniques are
used to reduce sub threshold leakage current. In sub-threshold SRAMs, power supply voltage
(VDD) is lower than the transistor threshold voltage (Vt) and the sub threshold leakage current
is the operating current.
Tae-Hyoung Kim introduced various circuit techniques for designing robust high-density sub
threshold SRAMs: (i) decoupled cell for read margin improvement, (ii) utilizing reverse short
channel effect (RSCE) for write margin improvement, (iii) eliminating data- dependent bit line
leakage to enable long bit lines, (iv) virtual ground replica scheme for improved bit line sensing
margin, (v) write back scheme for data preservation during write, and (vi) optimal gate sizing
based on sub threshold logical effort. To achieve all these operations the authors proposed 10T
SRAM cell.

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3.METHODOLOGY AND IMPLEMENTATION

3.1 Circuit Diagram with explanation :

SRAM Basics The memory circuit is said to be static if the stored data can be retained
indefinitely, as long as the power supply is on, without any need for periodic refresh
operation. The data storage cell, i.e., the one-bit memory cell in the static RAM arrays,
invariably consists of a simple latch circuit with two stable operating points. Depending
on the preserved state of the two inverter latch circuit, the data being held in the memory
cell will be interpreted either as logic '0' or as logic '1'. To access the data contained in
the memory cell via a bit line, we need atleast one switch, which is controlled by the
corresponding word line as shown in Figure

Fig. SRAM CELL

CMOS SRAM Cell :

A low power SRAM cell may be designed by using cross-coupled CMOS inverters. The most
important advantage of this circuit topology is that the static power dissipation is very small;
essentially, it is limited by small leakage current. Other advantages of this design are high noise
immunity due to larger noise margins, and the ability to operate at lower power supply voltage.
The major disadvantage of this topology is larger cell size. The circuit structure of the full
CMOS static RAM cell is shown in fig below. The memory cell consists of simple CMOS
inverters connected back to back, and two access transistors. The access transistors are turned
on whenever a word line is activated for read or write operation, connecting the cell to the
complementary bit line columns.

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Fig.Full CMOS SRAM Cell

CMOS SRAM Cell Design

To determine W/L ratios of the transistors, a number of design criteria must be taken into
consideration. The two basic requirements, which dictate W/L ratios, are that the data read
operation should not destroy the stored information in the cell. The cell should allow stored
information modification during write operation. In order to consider operations of SRAM, we
have to take into account, the relatively large parasitic column capacitance Cbit and Cbit_ and
column pull up transistors as shown in Figure

Fig.CMOS SRAM Cell with precharge capacitors

When none of the word lines is selected, the pass transistors M3 and M4 are turned off and the
data is retained in all memory cells. The column capacitances are charged by the pull-up
transistors P1 and P2. The voltages across the column capacitors reach VDD – V

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3.2 Component Description:

1. Inverter

Inverter using cmos:

An Inverter is a Logic Gate that has only one Input, it outputs the opposite Logic State of its
Input.

A Y
0 1
1 0

If the applied input is low then the output becomes high and vice versa. Inverters can be
constructed using a single NMOS transistor or a single PMOS transistor coupled with a resistor.
Since this 'resistive-drain' approach uses only a single type of transistor, it can be fabricated at
low cost. However, because current flows through the resistor in one of the two states, the
resistive-drain configuration is disadvantaged for power consumption and processing speed.
Alternatively, inverters can be constructed using two complementary transistors in
a CMOS configuration. This configuration greatly reduces power consumption since one of the
transistors is always off in both logic states.[1] Processing speed can also be improved due to the
relatively low resistance compared to the NMOS-only or PMOS-only type devices.

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NMOS:

N-type metal-oxide-semiconductor logic uses n-type field-effect transistors (MOSFETs) to

implement logic gates and other digital circuits. These nMOS transistors operate by creating
an inversion layer in a p-type transistor body. This inversion layer, called the n-channel, can
conduct electrons between n-type "source" and "drain" terminals. The n-channel is created by
applying voltage to the third terminal, called the gate. Like other MOSFETs, nMOS transistors
have four modes of operation: cut-off (or sub threshold), triode, saturation (sometimes called
active), and velocity saturation The MOSFETs are n-type enhancement mode transistors,
arranged in a so-called "pull-down network" (PDN) between the logic gate output and negative
supply voltage (typically the ground). A pull up (i.e. a "load" that can be thought of as a resistor,
see below) is placed between the positive supply voltage and each logic gate output. Any logic
gate, including the logical inverter, can then be implemented by designing a network of parallel
and/or series circuits, such that if the desired output for a certain combination of boolean input
values is zero (or false), the PDN will be active, meaning that at least one transistor is allowing
a current path between the negative supply and the output. This causes a voltage drop over the
load, and thus a low voltage at the output, representing the zero.

PMOS:

P-type metal-oxide-semiconductor logic uses p-channel metal-oxide-semiconductor field effect

transistors (MOSFETs) to implement logic gates and other digital circuits. PMOS transistors
operate by creating an inversion layer in an n-type transistor body. This inversion layer, called
the p-channel, can conduct holes between p-type "source" and "drain" terminals.
The p-channel is created by applying voltage to the third terminal, called the gate. Like other
MOSFETs, PMOS transistors have four modes of operation: cut-off (or sub threshold), triode,
saturation (sometimes called active), and velocity saturation.
While PMOS logic is easy to design and manufacture (a MOSFET can be made to operate as a
resistor, so the whole circuit can be made with PMOS FETs), it has several shortcomings as
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well. The worst problem is that there is a direct current (DC) through a PMOS logic gate when
the PUN is active, that is, whenever the output is high, which leads to static power dissipation
even when the circuit sits idle.
Also, PMOS circuits are slow to transition from high to low. When transitioning from low to
high, the transistors provide low resistance, and the capacitive charge at the output accumulates
very quickly (similar to charging a capacitor through a very low resistance). But the resistance
between the output and the negative supply rail is much greater, so the high-to-low transition
takes longer (similar to discharge of a capacitor through a high resistance). Using a resistor of
lower value will speed up the process but also increases static power dissipation.

Sense amplifier:

In modern computer memory, a sense amplifier is one of the elements which make up the
circuitry on a semiconductor memory chip (integrated circuit); the term itself dates back to the
era of magnetic core memory.[1] A sense amplifier is part of the read circuitry that is used when
data is read from the memory; its role is to sense the low power signals from a bitline that
represents a data bit (1 or 0) stored in a memory cell, and amplify the small voltage swing to
recognizable logic levels so the data can be interpreted properly by logic outside the memory.

3.3 Circuit Design:

A typical SRAM cell is made up of six MOSFETs. Each bit in an SRAM is stored on
four transistors (M1, M2, M3, M4) that form two cross-coupled inverters. This storage cell has
two stable states which are used to denote 0and 1. Two additional access transistors serve to
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control the access to a storage cell during read and write operations. In addition to such six-
transistor (6T) SRAM, other kinds of SRAM chips use 4, 8, 10 (4T, 8T, 10T SRAM), or more
transistors per bit. Four-transistor SRAM is quite common in stand-alone SRAM devices (as
opposed to SRAM used for CPU caches), implemented in special processes with an extra layer
of polysilicon, allowing for very high-resistance pull-up resistors.The principal drawback of
using 4T SRAM is increased static power due to the constant current flow through one of the
pull-down transistors.
This is sometimes used to implement more than one (read and/or write) port, which may be
useful in certain types of video memory and register file simply implemented with multi-ported
SRAM circuitry.
Generally, the fewer transistors needed per cell, the smaller each cell can be. Since the cost of
processing a silicon wafer is relatively fixed, using smaller cells and so packing more bits on
one wafer reduces the cost per bit of memory.Access to the cell is enabled by the word line (WL
in figure) which controls the two access transistors M5 and M6 which, in turn, control whether
the cell should be connected to the bit lines: BL and BL. They are used to transfer data for both
read and write operations. Although it is not strictly necessary to have two bit lines, both the
signal and its inverse are typically provided in order to improve noise margins.
During read accesses, the bit lines are actively driven high and low by the inverters in the SRAM
cell. This improves SRAM bandwidth compared to DRAMs – in a DRAM, the bit line is
connected to storage capacitors and charge sharing causes the bitline to swing upwards or
downwards.

3.4 Circuit Description:

The memory cell shown here forms the basis for most static random-access memories in CMOS
technology. It uses six transistors to store and access one bit. The four transistors in the center
form two cross-coupled inverters. In actual devices, these transistors are made as small as
possible to save chip-area, and are very weak. Due to the feedback structure, a low input value
on the first inverter will generate a high value on the second inverter, which amplifies (and
stores) the low value on the second inverter. Similarly, a high input value on the first inverter
will generate a low input value on the second inverter, which feeds back the low input value
onto the first inverter. Therefore, the two inverters will store their current logical value,
whatever value that is.

The two lines between the inverters are connected to two separate bitlines via two n-channel
pass-transistors (left and right of the cell). The gates of those transistors are driven by a
wordline. In a larger SRAM, the wordline is used to address and enable all bits of one memory
word. As long as the wordline is kept low, the SRAM cell is disconnected from the bitlines. The
inverters keep feeding themselves, and the SRAM stores its current value.

When the wordline is high, both n-channel transistors are conducting and connect the inverter
inputs and outputs to the two vertical bitlines. That is, the two inverters drive the current data
value stored inside the memory cell onto the bitline (left) and the inverted data value on the
inverted-bitline (right). This data can then be amplified and generates the output value of the
SRAM cell during a read operation.

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Consider a data read operation,assuming that logic '0' is stored in the cell. The transistors M2
and M5 are turned off, while the transistors M1 and M6 operate in linear mode. Thus internal
node voltages are V1 = 0 and V2 = VDD before the cell access transistors are turned on. The
active transistors at the beginning of data read operation are shown. After the pass transistors
M3 and M4 are turned on by the row selection circuitry, the voltage CBb of will not change any
significant variation since no current flows through M4. On the other hand M1 and M3 will
conduct a nonzero current and the voltage level of CB will begin to drop slightly. The node
voltage V1 will increase from its initial value of '0'V. The node voltage V1 may exceed the
threshold voltage of M2 during this process, forcing an unintended change of the stored state.
Therefore voltage must not exceed the threshold voltage of M2, so the transistor M2 remains
turned off during read phase. The transistor M3 is in saturation whereas M1 is linear.

Read operation

i. precharge BL and BL_bar to high

ii. Turn on WL
iii. BL or BL_bar are will be pulled down to low depending on the Q and Q_bar
iv. Ex.If Q=0 and Q_bar=1 ,BL discharges through M3 -M1-Gnd and BL_bar stays high
but Q bumps up slightly.

Write operation

Consider the write '0' operation assuming that logic '1' is stored in the SRAM cell initially.
Figure 28.51 shows the voltage levels in the CMOS SRAM cell at the beginning of the data
write operation. The transistors M1 and M6 are turned off, while M2 and M5 are operating in
the linear mode. Thus the internal node voltage V1 = VDD and V2 = 0 before the access transistors
are turned on. The column voltage Vb is forced to '0' by the write circuitry. Once M3 and M4
are turned on, we expect the nodal voltage V2 to remain below the threshold voltage of M1. The
voltage at node 2 would not be sufficient to turn on M1. To change the stored information, i.e.,

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to force V1 = 0 and V2 = VDD, the node voltage V1 must be reduced below the threshold voltage
of M2, so that M2 turns off. When V1=Vth the transistor M3 operates in linear region while
M5 operates in saturation region.

Write operation:
i. Drive BL and BL_bar with necessary values
ii. Turn on WL
iii. Bit lines overpower cell with new value
iv. Ex.Q=0, Q_bar=1 and BL= 1,BL_bar=0 this forces Q_bar to low and Q to high
v. To overpower feedback inverter loop M3 should be greater than M5

4.RESULTS AND DISCUSSION

Simulated circuit in cadence:

Noise margin graph:

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Parametric analysis:

Write operation circuit:

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Write operation

Discussion:
The potential stability problem of this design arises during read and writes operation, where the
cell is most vulnerable towards noise and thus the stability of the cell is affected. If the cell
structure is not designed properly, it may change its state during read and write operation.

5.CONCLUSION AND FUTURE WORKS

5.1 Conclusion:
The 65nm technologies SRAM is implemented with read and write assist circuit technique. The
project has been very challenging since it includes functional validation, transistor sizing, and
layout of various circuits. Full functionalities of all the design features have been validated.
Based on simulation results for the circuit it can be concluded that read and write assist circuitry
is effective controlling power dissipation. Finally, the power dissipation of both
the circuits incorporated is compared. Speed of the SRAM can be improved by scaling down
the technology.

5.2 FUTURE WORKS:

To perform the write operation in the SRAM cell to flip the data value, nearly full voltage
swings is required on the bit line. This full voltage swing on the highly capacitive bit lines will
consume a greater amount of power according to law of cv^2 Thus voltage swing reduction
is an effective way to decrease the power dissipation. The future course of action involves
effective reduction of leakage in an SRAM cell. It is proposed here that appropriate leakage
reduction techniques would be developed with an emphasis on the reduction of gate leakage.
Leakage reduction in SRAM is also possible using self-controllable switch either at the upper
end of the cell to reduce supply voltage or at the lower end of the cell to raise the potential of
the ground node .This method would also be tested for its efficacy when this work is advanced.

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REFERENCES:
Papers

1. Abhishek Agal et al Int. Journal of Engineering Research and Applications

2. IOSR Journal of VLSI and Signal Processing

Books / Reports

1. The 8051 Microcontroller and Embedded Systems using Assembly and C -by
Muhammad Ali Mazidi

2. Design of Analog CMOS Integrated Circuits, by Razavi.

Webpages

https://www.academia.edu/5234820/IMPLEMENTATION_AND_DESIGN_OF_6T-
SRAM_WITH_READ_AND_WRITE_ASSIST_CIRCUITS

http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.302.8449&rep=rep1&type=pdf

Youtube / any other reference

https://www.youtube.com/watch?v=k5VBJcUcaWU

https://www.youtube.com/watch?v=kTbJVQ-DEZk

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APPENDIX
< DATA sheets >

PMOS:

NMOS:

INVERTER

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<Photos captured during project execution>

Static noise margin:

Parametric analysis:

Circuit diagram:

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Write operation circuit

Write operation:

Any other information related to the project work

Static random access memory (SRAM) can retain its stored information as long as power is
supplied. This is in contrast to dynamic RAM (DRAM) where periodic refreshes are necessary
or non-volatile memory where no power needs to be supplied for data retention. The structure
of a 6 transistor SRAM cell, storing one bit of information. The core of the cell is formed by
two CMOS inverters, where the output potential of each inverter Vout is fed as input into the
other Vin. This feedback loop stabilizes the inverters to their respective state.

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