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This system is based on PCI architecture, which have standard hardware peripheral interface. The power
management complies with Advanced Configuration and Power Interface (ACPI) 1.0. It also provides easy
configuration through CMOS setup, which is built in system BIOS software and can be pop-up by pressing
F2 at system start up or warm reset. System also provides icon LEDs to display system status, such as power
indicator, HDD/CDROM, NUM LOCK, CAP LOCK, SCROLL LOCK, SUSPEND MODE and Battery
charging status. It also equipped 2 USB ports.
The memory subsystem supports 0MB on board memory, two JEDEC-standard 200-pin, small-outline, dual
in-line memory module (SODIMM), support PC2100 & PC2700.
SiS650 IGUI Host Memory Controller integrates a high performance host interface for Intel Pentium 4
processor, a high performance 2D/3D Graphic Engine, a high performance memory controller, an AGP 4X
interface, and SiS MuTIOL® Technology connecting w/ SiS961 MuTIOL® Media I/O.
The CH7019 is a Display Controller device which accepts two digital graphics input data streams. One data
stream outputs through an LVDS transmitter to an LCD panel, while the other data stream is encoded for NTSC
or PALTV and outputs through a 10-bit high speed DAC. The TV encoder device encodes a graphics signal up
to 1024 x 768 resolution and outputs the video signals according to NTSC or PAL standards. The LVDS
transmitter operates at pixel speeds up to 165MHz per link, supporting 1600 x 1200 panels at 60Hz refresh rate.
The TI PCI4410 is a dual-function PCI device compliant with PCI Local Bus Specification 2.2. Function 0
provides the independent PC Card socket controller compliant with the 1997 PC Card Standard. The PCI4410
provides features that make it the best choice for bridging between the PCI bus and PC Cards, and supports
either 16-bit or CardBus PC Cards in the socket, powered at 5 V or 3.3 V, as required.
Function 1 of the PCI4410 is compatible with IEEE1394A and the latest 1394 open host controller interface
(OHCI) specifications. The chip provides the IEEE1394 link function and is compatible with data rates of 100,
200, and 400Mbits per second. Deep FIFOs are provided to buffer 1394 data and accommodate large host bus
latencies.
To provide for the increasing number of multimedia applications, the AC97 CODEC ALC201 is integrated
onto the motherboard.
A full set of software drivers and utilities are available to allow advanced operating systems such as Windows
Me and Windows 2000 to take full advantage of the hardware capabilities such as bus mastering IDE, Windows
95-ready Plug & Play, Advanced Power Management (APM) and Advance configuration and power interface
(ACPI).
Following chapters will have more detail description for each individual sub-systems and functions.
CPU Intel® Pentium® 4 processor; Willamette/Northwood with mFCPGA2 Package, mPGA 478
Socket
Support up to Willamette P4 1.7GHz (Throttling) / Northwood above 2.0 GHz(Throttling)
FSB 400MHz /PC 2100/1600
Core logic SiS 650+SiS961: Host & Memory & AGP Controller integrates a high performance host
interface for Intel Pentium 4 processor, a high performance memory controller, a AGP
interface, and SiS MuTIOL® Technology connecting w/ SiS961 MuTIOL® Media IO.
VGA Control Chrontel CH7019
System BIOS 256KB Flash EPROM
Inside -Includes System BIOS, VGA BIOS, and plug & Play capability, ACPI
Memory 0MB on board memory
-Two JEDEC-standard 200-pin, small-outline, dual in-line memory module (SODIMM)
-Support PC2100 & PC2700
Video Memory 8/16/32/64 UMA
Clock Generator ICS 952001
DDR Clock Buffer ICS 93722
Embedded controller Hitachi H8 3437S
PCMCIA Card Bus Controller: TI PCI 4410,One type II slot Card Bus
TSB41AB1 of 1394 PHY
Audio System AC97 CODEC: Advance Logic, Inc, ALC201
Power Amplifier: TI TPA0202
Super I/O PC87393
IR Module for HP3600
Modem 56Kbps(V.90, worldwide) MDC Modem
PHY of LAN ICS1893Y-10 10/100 base T PHY
The Intel NetBurst micro-architecture delivers a number of new and innovative features including Hyper
Pipelined Technology, 400 MHz System Bus, Execution Trace Cache, and Rapid Execution Engine as well as
a number of enhanced features Advanced Transfer Cache, Advanced Dynamic Execution, Enhanced Floating-
point and Multi-media Unit, and Streaming SIMD Extensions 2. Many of these new innovations and advances
were made possible with improvements in processor technology, process technology, and circuit design that
could not previously be implemented in high-volume, manufacturable solutions. The features and resulting
benefits of the new micro-architecture are defined below.
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11
12
Recommended Application:
Output features:
13
Key Specifications:
14
Recommended Application:
Product description/features:
Low skew, low jitter PLL clock driver
I2 C for functional and output control
Feedback pins for input to output synchronization
Spread Spectrum tolerant inputs
3.3V tolerant CLK_INT input
Switching Characteristics
SiS650 IGUI Host Memory Controller integrates a high performance host interface for Intel Pentium 4
processor, a high performance 2D/3D Graphic Engine, a high performance memory controller, an AGP 4X
interface, and SiS MuTIOL® Technology connecting w/ SiS961 MuTIOL® Media IO.
SiS650 Host Interface features the AGTL & AGTL+ compliant bus driver technology with integrated on-
die termination to support Intel Pentium 4 processors. SiS650 provides a 12-level In-Order-Queue to support
maximum outstanding transactions up to 12. It integrated a high performance 2D/3D Graphic Engine, Video
Accelerator and Advanced Hardware Acceleration MPEGI/MPEGII Video Decoder for the Intel Pentium 4
series based PC systems. It also integrates a high performance 2.1GB/s DDR266 Memory controller to sustain
the bandwidth demand from the integrated GUI or external AGP master, host processor, as well as the multi
I/O masters. In addition to integrated GUI, SiS650 also can support external AGP slot with AGP 1X/2X/4X
capability and Fast Write Transactions. A high bandwidth and mature SiS MuTIOL® technology is
incorporated to connect SiS650 and SiS961 MuTIOL® Media I/O together. SiS MuTIOL® technology is
developed into three layers, the Multi-threaded I/O Link Layer delivering 1.2GB bandwidth to connect
embedded DMA Master devices and external PCI masters to interface to Multi-threaded I/O Link layer, the
Multi-threaded I/O Link Encoder/Decoder in SiS961 to transfer data w/ 533 MB/s bandwidth from/to Multi-
threaded I/O Link layer to/from SiS650, and the Multi-threaded I/O Link Encoder/Decoder in SiS650 to
transfer data w/ 533 MB/s from/to Multi-threaded I/O Link layer to/from SiS961.
16
The Integrated GUI features a high performance 3D accelerator with 2 Pixel / 4 Texture, and a 128 bit 2D
accelerator with 1T pipeline BITBLT engine. It also features a Video Accelerator and advanced hardware
acceleration logic to deliver high quality DVD playback. A Dual 12 bit DDR digital video link interfaced to
SiS 301B Video Bridge packaged in 100-pin PQFP is incorporated to expand the SiS650 functionality to
support the secondary display, in addition to the default primary CRT display. The SiS301B Video Bridge
integrates an NTSL/PAL video encoder with Macro Vision Ver. 7.1.L1 option for TV display, a TMDS
transmitter with Bi-linear scaling capability for TFT LCD panel support, and an analog RGB port to support a
secondary CRT. The primary CRT display and the extended secondary display (TV, TFT LCD Panel, 2'nd
CRT) features the Dual View Capability in the sense that both can generate the display in independent
resolutions, color depths, and frame rates.
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The Integrated Audio Controller features a 6 channels of AC 97 v2.2 compliance audio to present 5.1-
channel Dolby digital material or to generate stereo audio with simultaneous V.90 HSP modem operation.
Besides, 4 separate SDATAIN pins are provided to support multiple audio Codecs + one modem Codec
maximally, effectuating the realization of 5.1 channel Dolby digital material in theater quality sound. Both
traditional consumer digital audio channel as well as the AC 97 v2.2 compliant consumer digital audio slot are
supported. VRA mode is also associated with both the AC 97 audio link and the traditional consumer digital
audio channel.
The integrated Fast Ethernet MAC features an IEEE 802.3 and IEEE 802.3x compliant MAC supporting
full duplex 10 Base-T, 100 Base-T Ethernet, or 1Mb/s & 10Mb/s Home networking. 5 wake-up Frames,
Magic Packet and link status change wake-up functions in G1/G2 states are supported. Besides, the integrated
MAC provides a scheme to store the MAC address without the need of an external EEPROM. The 25 MHz
oscillating circuit is integrated so as only an external low cost 25 MHz crystal is needed for the clocking
system.
19
The integrated power management module incorporates the ACPI 1.0b compliance functions, the APM 1.2
compliance functions, and the PCI bus power management interface spec. v1.1. Numerous power-up events
and power down events are also supported. 21 general purposed I/O pins are provided to give an easy to use
logic for specific application. In addition, the SiS961 supports Intel Speed Step technology and Deeper Sleep
power state for Intel Mobile processor. For AMD processor, the SiS961 use the CPUSTP# signal to reduce
processor voltage during C3 and S1 state.
20
The CH7019 is a Display Controller device which accepts two digital graphics input data streams. One data
stream outputs through an LVDS transmitter to an LCD panel, while the other data stream is encoded for NTSC
or PALTV and outputs through a 10-bit high speed DAC. The TV encoder device encodes a graphics signal up
to 1024x768 resolution and outputs the video signals according to NTSC or PAL standards. The LVDS
transmitter operates at pixel speeds up to 165MHz per link, supporting 1600x1200 panels at 60Hz refresh rate.
The device can also accept one graphics data stream over two 12-bit wide variable voltage ports which support
nine different data formats including RGB and YCrCb (RGB must be used for LVDS output). A maximum of
330M pixels per second can be output through dual LVDS links.
The TV-Out processor will perform non-interlaced to interlaced conversion with scaling, flicker filtering, and
encoding into any of the NTSC or PAL video standards. The scaler and flicker filter are adaptive and
programmable for superior text display. Eight graphics resolutions are supported up to 1024 by 768 with full
vertical and horizontal under-scan capability in all modes. A high accuracy low jitter phase locked loop is
integrated to create outstanding video quality. Support is provided for MacrovisionTM. In addition to TV
encoder modes, bypass modes are included which allow the TV DAC’s to be used as a second CRT DAC .
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All card signals are internally buffered to allow hot insertion and removal without external buffering. The
PCI4410 is register compatible with the IntelTM 82365SLF and 82365SL ExCA controllers. The PCI4410
internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for
maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed
performance level with sustained bursting. The PCI4410 can be programmed to accept posted writes to
improve bus utilization.
Function 1 of the PCI4410 is compatible with IEEE1394A and the latest 1394 open host controller interface
(OHCI) specifications. The chip provides the IEEE1394 link function and is compatible with data rates of 100,
200, and 400Mbits per second. Deep FIFOs are provided to buffer 1394 data and accommodate large host bus
latencies. The PCI4410 provides physical write posting and a highly tuned physical data path for SBP-2
performance. Multiple cache line burst transfers, advanced internal arbitration, and bus holding buffers on the
PHY/Link interface are other features that make the PCI4410 the best-in-class 1394 Open HCI solution.
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Various implementation-specific functions and general-purpose inputs and outputs are provided through eight
multifunction terminals. These terminals present a system with options in PC/PCI DMA, PCI LOCK and
parallel interrupts, PC Card activity indicator LEDs, and other platform-specific signals. ACPI-compliant
general-purpose events may be programmed and controlled through the multifunction terminals, and an ACPI-
compliant programming interface is included for the general-purpose inputs and outputs.
The PCI4410 is compliant with the latest PCI Bus Power Management Specification, and provides several low-
power modes which enable the host power system to further reduce power consumption. The PC Card
(CardBus) Controller and IEEE 1394 Host Controller Device Class Specifications required for Microsoft
OnNowTM power management are supported. Furthermore, an advanced complementary metal-oxide
semiconductor (CMOS) process achieves low system power consumption.
Unused PCI4410 inputs must be pulled to a valid logic level using a 43-kΩ resistor.
26
Interface to parallel single-slot PC Card power interface switches like the TITM TPS2211
Up to five general-purpose I/Os
Programmable output select for CLKRUN\
Five PCI memory windows and two I/O windows available to the 16-bit PC Card socket
Two I/O windows and two memory windows available to the CardBus socket
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The TPS2211A PC Card power-interface switch provides an integrated power-management solution for a
single PC Card. All of the discrete power MOSFETs, a logic section, current limiting, and thermal protection
for PC Card control are combined on a single integrated circuit, using the Texas Instruments LinBiCMOSTM
process. The circuit allows the distribution of 3.3-V, 5-V, and/or 12-V card power, and is compatible with
many PCMCIA controllers. The current-limiting feature eliminates the need for fuses, which reduces
component count and improves reliability. Current-limit reporting can help the user isolate a system fault to
the PC Card.
The TPS2211A features a 3.3-V low-voltage mode that allows for 3.3-V switching without the need for 5 V.
Bias power can be derived from either the 3.3-V or 5-V inputs. This facilitates low-power system designs
such as sleep mode and pager mode where only 3.3 V is available.
End equipment for the TPS2211A includes notebook computers, desktop computers, personal digital assistants
(PDAs), digital cameras, and bar-code scanners.
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Fully Integrated VCC and Vpp Switching for Single-Slot PC CardTM Interface
Low rDS(on) (70-m 5-V VCC Switch and 3.3-V VCC Switch)
Compatible With Industry-Standard Controllers
3.3-V Low-Voltage Mode
Meets PC Card Standards
12-V Supply Can Be Disabled Except During 12-V Flash Programming
Short-Circuit and Thermal Protection
Space-Saving 16-Pin SSOP (DB)
Compatible With 3.3-V, 5-V, and 12-V PC Cards
Break-Before-Make Switching
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The TSB41AB1 requires only an external 24.576-MHz crystal as a reference. An external clock may be
provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which
generates the required 393.216-MHz reference signal. This reference signal is internally divided to provide
the clock signals used to control transmission of the outbound encoded strobe and data information. A 49.152-
MHz clock signal is supplied to the associated LLC for synchronization of the two chips and is used for
resynchronization of the received data. The power-down (PD) function, when enabled by asserting the PD
terminal high, stops operation of the PLL.
The TSB41AB1 supports an optional isolation barrier between itself and its LLC. When the ISO\ input
terminal is tied high, the LLC interface outputs behave normally. When the ISO\ terminal is tied low, internal
differentiating logic is enabled, and the outputs are driven such that they can be coupled through a capacitive
or transformer galvanic isolation barrier as described in Annex J of IEEE Std 1394-1995 and in IEEE 1394a-
2000 (section 5.9.4) (hereinafter referred to as Annex J type isolation). To operate with TI bus holder isolation
the ISO/terminal on the PHY must be high.
31
During packet reception the TPA and TPB transmitters of the receiving cable port are disabled, and the
receivers for that port are enabled. The encoded data information is received on the TPA cable pair, and the
encoded strobe information is received on the TPB cable pair. The received data-strobe information is decoded
to recover the receive clock signal and the serial data bits. The serial data bits are split into two-, four-, or eight-
bit parallel streams (depending upon the indicated receive speed), resynchronized to the local 49.152-MHz
system clock and sent to the associated LLC.
Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during
initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the
arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this
common-mode voltage is used during arbitration to set the speed of the next packet transmission. In addition,
the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the
remotely supplied twisted-pair bias voltage.
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The line drivers in the TSB41AB1 operate in a high-impedance current mode, and are designed to work with
external 112Ω. line-termination resistor networks in order to match the 110Ω. cable impedance. One network
is provided at each end of a twisted-pair cable. Each network is composed of a pair of series-connected 56Ω.
resistors. The midpoint of the pair of resistors that is directly connected to the twisted-pair-A terminals is
connected to its corresponding TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly
connected to the twisted-pair-B terminals is coupled to ground through a parallel R-C network with
recommended values of 5kΩ and 220pF. The values of the external line termination resistors are designed to
meet IEEE Std 1394-1995 when connected in parallel with the internal receiver circuits. An external resistor
connected between the R0 and R1 terminals sets the driver output current, along with other internal operating
currents. This current-setting resistor has a value of 6.34kΩ± 1.0%.
When the power supply of the TSB41AB1 is off while the twisted-pair cables are connected, the TSB41AB1
transmitter and receiver circuitry presents a high impedance to the cable and does not load the TPBIAS voltage
at the other end of the cable. Fail-safe circuitry blocks any leakage path from the port back to the device power
plane.
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Four package terminals are used as inputs to set the default value for four configuration status bits in the self-
ID packet, and are tied high through a 1kΩ resistor or hardwired low as a function of the equipment design.
The PC0 C2 terminals are used to indicate the default power-class status for the node (the need for power from
the cable or the ability to supply power to the cable). See Table 9 for power-class encoding. The C/LKON
terminal is used as an input to indicate that the node is a contender for either isochronous resource manager
(IRM) or for bus manager (BM).
The TSB41AB1 supports suspend/resume as defined in the IEEE 1394a-2000 specification. The suspend
mechanism allows pairs of directly connected ports to be placed into a low-power state (suspended state) while
maintaining a port-to-port connection between bus segments. While in the suspended state, a port is unable to
transmit or receive data transaction packets. However, a port in the suspended state is capable of detecting
connection status changes and detecting incoming TPBIAS. When the port of the TSB41AB1 is suspended, all
circuits except the band gap reference generator and bias detection circuit is powered down, resulting in
significant power savings. For additional details of suspend/resume operation see IEEE 1394a-2000. The use of
suspend/resume is recommended for new designs.
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The cable-not-active (CNA) output terminal (64-terminal PAP package only) is asserted high when there are no
twisted-pair cable ports receiving incoming bias (that is, they are either disconnected or suspended), and can be
used along with LPS to determine when to power down the TSB41AB1. The CNA output is not debounced.
When the PD terminal is asserted high, the CNA detection circuitry is enabled (regardless of the previous state
of the ports) and a pulldown is activated on the RESET\ terminal so as to force a reset of the TSB41AB1
internal logic.
The LPS (link power status) terminal works with the C/LKON terminal to manage the power usage in the node.
The LPS signal from the LLC is used in conjunction with the LCtrl bit to indicate the active/power status of the
LLC. The LPS signal is also used to reset, disable, and initialize the PHY-LLC interface (the state of the PHY-
LLC interface is controlled solely by the LPS input, regardless of the state of the LCtrl bit).
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When the PHY-LLC interface is in the low-power disabled state, the TSB41AB1 automatically enters a low-
power mode if the port is inactive (disconnected, disabled, or suspended). In this low-power mode, the
TSB41AB1 disables its internal clock generators and also disables various voltage and current reference
circuits depending on the state of the port (some reference circuitry must remain active in order to detect new
cable connections, disconnections, or incoming TPBIAS, for example). The lowest power consumption (the
ultralow-power sleep mode) is attained when the port is either disconnected, or disabled with the port interrupt
enable bit cleared. The TSB41AB1 exits the low-power mode when the LPS input is asserted high or when a
port event occurs which requires that the TSB41AB1 become active in order to respond to the event or to
notify the LLC of the event (for example, incoming bias is detected on a suspended port, a disconnection is
detected on a suspended port, a new connection is detected on a nondisabled port, etc.). The SYSCLK output
becomes active (and the PHY-LLC interface is initialized and becomes operative) within 7.3 ms after LPS is
asserted high when the TSB41AB1 is in the low-power mode.
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CPS
LPS Received Data
ISO Decoder/Retimer
Link
CNA Interface
I/O
SYSCLK
LREQ TPA+
CTL0 TPA-
CTL1
D0
D1
D2
D3
D4 Arbitration TPB+
D5 and Control TPB-
D6 State Machine
D7 Logic
PC0
PC1
PC2
CLKON
R0 Bias Voltage
R1 and
Current
TPBIAS Generator
Crystal
XI
Transmit Data Oscillator
XO
Encoder PLL System,
PD FILTER0
and Clock FILTER1
RESET Generator
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Fully supports provisions of IEEE 1394-1995 standard for high performance serial bus and IEEE 1394a-2000
Fully interoperable with firewire™ and i.LINK™ implementation of IEEE Std 1394
Fully compliant with openHCI requirements
Provides one IEEE 1394a-2000 fully compliant cable port at 100/200/400 megabits per second (Mbits/s)
Full IEEE 1394a-2000 support includes: connection debounce, arbitrated short reset, multispeed concatenation,
arbitration acceleration, fly-by concatenation, port disable/suspend/resume
Register bits give software control of contender bit, power class bits, link active control bit, and IEEE
1394a- 2000 Features
IEEE 1394a-2000 compliant common mode noise filter on incoming TPBIAS
Extended resume signaling for compatibility with legacy DV devices, and terminal- and register- compatibility
with TSB41LV01, allow direct isochronous transmit to legacy DV devices with any link layer even when root
Power-Down features to conserve energy in battery powered applications include: automatic device power
down during suspend, device power-down terminal, link interface disable via LPS, and inactive ports
powered down
Failsafe circuitry senses sudden loss of power to the device and disables the port to ensure that the device
does not load TPBIAS of the connected device and blocks any leakage path from the port back to
the device power plane
Software device Reset (SWR)
Industry leading low power consumption
Ultralow-power sleep mode
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The ALC201 is an AC97 2.2 compatible stereo audio codec designed for PC multimedia systems.The
ALC201 provides the way for PC98 and PC99-compliant desktop, portable and entertainment PCs, where
high-quality audio is required. The ALC201 AC’97 CODEC provides a complete high quality audio solution.
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Single chip audio CODEC with high S/N ratio (>90 dB)
18-bit ADC and DAC resolution
Compliant with AC’97 2.2 specification
Meet performance requirements for audio on PC2001 systems
18-bit stereo full-duplex CODEC with independent and variable sampling rate
4 analog line-level stereo input with 5-bit volume control: LINE_IN, CD, VIDEO, AUX
2 analog line-level mono input: PC_BEEP, PHONE_IN
Mono output with 5-bit volume control
Stereo output with 5-bit volume control
2 MIC inputs: Software selectable
Power management
3D Stereo Enhancement
Headphone output with 50mW/20ohm driving capability (ALC201)
Line output with 50mW/20ohm driving capability (ALC201A)
Headphone jack-detect function to mute LINE output
Multiple CODEC extension
MC’97 chained in allowed for multi-channel application
External Amplifier power down capability
Support S/PDIF out is fully compliant with AC’97 specification rev2.2
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PC-TEL has streamlined the traditional modem into the Host Signal Processing (HSP) solution. Operating
with the Pentium class processors, HSP becomes part of the host computer’s system software. It requires less
power to operate and less physical space than standard modem solutions. PC-TEL’s HSP modem is an easily
integrated, cost-effective communications solution that is flexible enough to carry you into the future.
The PCT2303W chip set is an integrated direct access arrangement (DAA) and Codec that provides a
programmable line interface to meet international telephone line requirements. The PCT2303W chip set is
available in two 16-pin small outline packages (AC’97 interface on PCT303A and phone-line interface on
PCT303W). The chip set eliminates the need for an AFE, an isolation transformer, relays, opto-isolators, and
2-to 4-wire hybrid. The PCT2303W chip set dramatically reduces the number of discrete components and cost
required to achieve compliance with international regulatory requirements. The PCT2303W complies with
AC’97 Interface specification Rev. 2.1.
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Compatibility
ITU-T V.90 56000, 54667, 53333,52000, 50667, 49333, 48000,
46667, 45333, 42667, 41333, 40000, 38667, 37333,
36000, 34667, 33333, 32000, 30667, 29333, 28000bps
K56Flex 56000, 54000, 52000, 50000, 48000, 46000, 44000,
42000, 40000, 38000, 36000, 32000bps
ITU-T V.34Annex 33600,31200 bps
ITU-T V.34 28800 bps
ITU-T V.32bis 14400 bps
ITU-T V.32 9600,4800 bps
ITU-T V.22bis 2400 bps
ITU-T V.22 1200 bps
ITU-T V.21 300 bps
ITU-T V.23 1200/75 bps
43
Modulation
56000bps(V90&K56Flex) PCM
33600 bps (V.34Annex) TCM
28800 bps (V.34) TCM
14400 bps (V.32bis) TCM
12000 bps (V.32bis) TCM
9600 bps (V.32bis) TCM
7200 bps (V.32bis) QAM
9600 bps (V.32) TCM, QAM
4800 bps (V.32) QAM
14400 bps (V.17) TCM
12000 bps (V.17) TCM
9600 bps (V.29) QAM
7200 bps (V.29) QAM
4800 bps (V.27ter) DPSK
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Data Compression
V.42bis, MNP5
Error Correction
V.42 LAPM, MNP 2-4
DTE interface
45
46
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General Description
The ICS1893 is a low-power, physical-layer device (PHY) that supports the ISO/IEC 10Base-T and 100Base-
TXCarrier-Sense Multiple Access/Collision Detection (CSMA/CD) Ethernet standards. The ICS1893
architecture is based on the ICS1892. The ICS1893 supports managed or unmanaged node, repeater, and switch
applications.
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The ICS1893 provides a Serial Management Interface for exchanging command and status information with a
Station Management (STA) entity.
The ICS1893 Media Dependent Interface (MDI) can be configured to provide either half- or full-duplex
operation at data rates of 10 MHz or 100 MHz. The MDI configuration can be established manually (with input
pins or control register settings) or automatically (using the Auto-Negotiation features). When the ICS1893
Auto-Negotiation sublayer is enabled, it exchanges technology capability data with its remote link partner and
automatically selects the highest-performance operating mode they have in common.
Features
Supports category 5 cables with attenuation in excess of 24 dB at 100 MHz across a temperature range
from -5 to +85 C
DSP-based baseline wander correction to virtually eliminate killer packets across temperature range
from -5 to +85 C
51
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53
1. None
2. Standby
3. Off
4. Hibernate (must enable hibernate function in power management)
54
55
Battery Warning: Capacity below 10%, Battery Capacity LED flashes per second, system beeps per 2 seconds.
System will suspend to HDD after 2 Minutes to protect users data.
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57
1.4.3 HDD
Hitachi 30GB
Height: 9.5 mm, 2.5”
58
1.4.6 Keyboard
Windows 98 Keyboard, 1 color, multi languages support JP, US and Europe Keyboard with “ Volume UP ”
and “ Volume Down ” word.
59
1.4.8 Fan
HY45J05-001
1.4.9 Memory
DDR-RAM/ATP//128M/256M
DDR-RAM/Apacer//128M/256M
DDR-RAM/Unidorsa//128M/256M
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Doze Mode
In this mode, CPU will be toggling between on & stop grant mode either. The technology is clock throttling.
This can save battery power without loosing much computing capability. The CPU power consumption and
temperature is lower in this mode.
Standby mode
For more power saving, it turns of the peripheral components. In this mode, the following is the status of each
device:
CPU: Stop grant
LCD: backlight off
HDD: spin down
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Suspend to HDD:
All devices are stopped clock and power-down
System status is saved in HDD
All system status will be restored when powered on again
GPIO0 MB_ID0 I/O Main Driven Defined Driven Defined Driven Defined Off Off
GPIO1 LDRQ1# CD_IN# I/O Main Driven Defined Driven Defined Driven Defined Off Off
GPIO2 THERM# SB_THRM# I/O Main Driven Defined Driven Defined Driven Defined Off Off
GPIO3 EXTSMI# EXTSMI# I/O Main Driven Defined Driven Defined Driven Defined Off Off
GPIO4 CLKRUN# CLKRUN# I/O Main Driven Defined Driven Defined Driven Defined Off Off
GPIO5 PREQ5# LCD_ID0 I/O Main Driven Defined Driven Defined Driven Defined Off Off
GPIO6 PGNT5# LCD_ID1 I/O Main Driven Defined Driven Defined Driven Defined Off Off
GPIO7 LCD_ID2 I/O AUX Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined
GPIO8 RING# WAKEUP# I/O AUX High-Z High-Z High-Z High-Z High-Z
GPIO9 AC_SDIN2 SCI# I/O AUX High-Z High-Z High-Z High-Z High-Z
GPIO10 AC_SDIN3 CRT_IN# I/O AUX High-Z High-Z High-Z High-Z High-Z
GPIO11 SPK_OFF I/O AUX Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined
GPIO12 CPUSTP# CPU_STP# I/O AUX Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined
MPCIACT#
GPIO13 DPRSLPVR /DPRSLPVR I/O AUX Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined
GPIO14 CD_PWRON# I/O AUX Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined
GPIO15 VR_HILO# VR_HILO# I/O AUX Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined
GPIO16 LO_HI# LO_HI# OD AUX Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined
GPIO17 VGATEM# VGATEM# I/O AUX Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined
GPIO18 PMCLK CD_RST O AUX Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined
64
65
Port 3 TTL input voltage (input high min=2V, input low max=0.8V)
P30/HDB0/D0 82 ISA SD0 T I/O I/O I/O Keep ISA DATA bit 0
P31/HDB1/D1 83 ISA SD1 T I/O I/O I/O Keep ISA DATA bit 1
P32/HDB2/D2 84 ISA SD2 T I/O I/O I/O Keep ISA DATA bit 2
P33/HDB3/D3 85 ISA SD3 T I/O I/O I/O Keep ISA DATA bit 3
P34/HDB4/D4 86 ISA SD4 T I/O I/O I/O Keep ISA DATA bit 4
P35/HDB5/D5 87 ISA SD5 T I/O I/O I/O Keep ISA DATA bit 5
P36/HDB6/D6 88 ISA SD6 T I/O I/O I/O Keep ISA DATA bit 6
P37/HDB7/D7 89 ISA SD7 T I/O I/O I/O Keep ISA DATA bit 7
66
67
P62/KEYIN2/FTIA 28 KEY IN2 T↑ I I I Keep Key matrix input 2 need pull high
P63/KEYIN3/FTIB 29 KEY IN3 T↑ I I I Keep Key matrix input 3 need pull high
P64/KEYIN4/FTIC 32 KEY IN4 T↑ I I I Keep Key matrix input 4 need pull high
P65/KEYIN5/FTID 33 KEY IN5 T↑ I I I Keep Key matrix input 5 need pull high
P66/KEYIN6/IRQ6 34 KEY IN6 T↑ I I I Keep Key matrix input 6 need pull high
P67/KEYIN7/IRQ7 35 KEY IN7 T↑ I I I Keep Key matrix input 7 need pull high
Port 7 TTL input voltage (input high min=2V, input low max=0.8V)
68
P93/RD 22 K/M DATA T↑ I/O I/O I/O Keep need pull high
P94/WR 19 M DATA T↑ I/O I/O I/O Keep need pull high
P95/AS 18 H8/T DATA T↑ I/O I/O I/O Keep need pull high
P96/0 17 ENABKL T↑ I I I T Read H8 send A20gate status
P97/WAIT/SDA 16 BAT DATA T↑ I/O I/O I/O Keep SM BUS clock need pull high 5→3V
↑ Pull High
↓ Pull Low
5→3V Level shift
69
CPU Intel Pentium 4 Processors Willamette/Northwood with mFCPGA2 Package, mPGA478 Socket
Support up to Willamette P4 1.7GHz (Throttling) / Northwood above 2.0 GHz(Throttling)
FSB 400MHz / PC 2100
Chipset SiS650 + SiS961
L2 Cache 256KB
System BIOS Flash EPROM (Include System BIOS and VGA BIOS)
ACPI 1.0b; DMI 2.3.1 compliant
Memory 0MB SDRAM on board; Expandable to 1024MB
Expandable with combination of optional 128MB/256MB/512MB memory
Two 200-pin DDR SDRAM Memory Module, PC 2100/1600 specifications
ROM Drive 12.7mm Height
24X CD ROM Drive
8X DVD ROM Drive
8X4x24 CD-RW or above
8X8X4X24 Combo or above
HDD 2.5x9.5 mm height: 10/15/20/30GB; Support Ultra DMA 66/100
Reseller Exchangeable
Ext. FDD Support External FDD w/z USB I/F; 3.5" Format for 720KB/1.2MB/1.44MB
Display 14.1”/ 15” XGA TFT display; Resolution: 1024 x 768
14.1”/15” SXGA+ TFT display; Resolution: 1280 x 1024 (P)
70
71
72
73
n o
74
75
NOTE: Before you start to install/replace these modules, disconnect all peripheral devices and make sure the
notebook is not turned on or connected to AC power.
76
Reassembly
1. Push the battery pack into the compartment. The battery pack should be correctly connected when you
hear a clicking sound.
2. Slide the release lever to the “lock” ( ) position.
77
Figure 2-2 Insert a rod easy to remove Figure 2-16 Remove easy start
buttons cover
78
Reassembly
1. Reconnect the keyboard cable and fit the keyboard back into place with three screws.
2. Replace the easy start buttons cover.
79
Figure 2-6 Remove the cover and rail Figure 2-7 Remove the heatsink
80
Figure 2-8 Remove the fan’s power cord Figure 2-9 Remove the CPU
Reassembly
1. Carefully, align the arrowhead corner of the CPU with the beveled corner of the socket, then insert CPU
pins into the holes. Place the lever back to the horizontal position and push the lever to the left.
2. Connect the fan’s power cord to the system board, fit the heatsink onto the top of the CPU and secure with
four screws.
3. Replace the keyboard .Then replace easy start buttons cover.
81
Figure 2-10 Remove HDD module Figure 2-11 Disassemble the hard disk
Reassembly
1. To install the hard disk drive, place it in the bracket and secure with six screws.
2. Slide the HDD module into the compartment and secure with one screw.
82
Reassembly
1. Push the CD/DVD-ROM drive into the compartment.
2. Secure the CD/DVD-ROM drive with one screw.
83
Figure 2-13 Remove the SO-DIMM cover Figure 2-14 Remove the SO-DIMM
Reassembly
1. To install the SO-DIMM, match the SO-DIMM’s notched part with the socket’s projected part and firmly
insert the OS-DIMM into the socket at 20-degree angle. Then push down until the retaining clips lock the
SO-DIMM into cover.
2. Replace the SO-DIMM cover.
3. Replace seven screws to fasten the SO-DIMM socket cover.
84
Figure 2-15 Remove the LCD hinge cover Figure 2-16 Remove cables and screws
and button board to separate LCD
Reassembly
1. Attach the LCD assembly to the base unit and secure with four screws on the hinges.
2. Reconnect the LCD cable connectors to the system board.
3. Fit the easy start button board and secure with tow screws.
4. Replace two hinge cover, the heatsink, keyboard and easy start buttons cover.
85
Figure 2-17 Remove LCD frame Figure 2-18 Remove LCD panel
86
87
Reassembly
1. Fit the inverter board back into place and secure with one screw.
2. Reconnect the cable.
3. Replace the LCD frame. (See section 2.2.8 Reassembly)
4. Replace the LCD assembly. (See section 2.2.7 Reassembly)
88
Figure 2-20 Remove the bottom Figure 2-21 Remove the speaker assembly
89
Figure 2-22 Remove the base unit cover Figure 2-23 Remove the metal shield
90
Figure 2-24 Remove the screws and Figure 2-25 Remove the system board
disconnect the cable
Reassembly
1. Reconnect the cable to system board.
2. Replace four screws fasten the system board.
3. Reconnect one cable of system board fan and one cable of little battery to system board.
4. Replace four screws fasten the base unit.
5. Reconnect the touch pad cord.
6. Replace the base unit cover and secure with nine screws
7. Carefully put the notebook upside down. Then replace the bottom frame and secure with fourteen screws.
8. Replace the battery pack, LED panel, keyboard, CPU, HDD module, CD/DVD-ROM drive and LCD assembly.
91
Reassembly
1. Replace the touch-pad holder and touch-pad panel, and secure with eight screws.
2. Assemble the base unit cover. (See section 2.2.10 Reassembly)
92
Reassembly
1. Reconnect the cable to the modem card and secure the modem card with two screws.
2. Assemble the notebook. (See section 2.2.10 Reassembly)
93
94
J12
J7 J4
J18 : MDC Connector
J14 J25
J6
J5 VR1 J19 : Primary IDE Connector
J18 J21
J20
J24 J20 : Touch-pad Connector
J1
J2
J13 J28 J21 : Internal Micro Phone Jack
J27 J23 : L Speaker Connector
J19
J3
J8
J24 : Line Out Phone Jack
J11
J25 : R Speaker Connector
J23
J27 : IEEE1394 Port
J28 : External Microphone Jack
VR1 : Volume Control
J9
J509
95
J506 J505
U6 U5 U3
96
J1 : TV Out Jack
J2 : Power Jack (AC adapter)
SW1
J3 : Parallel Port Connector
J3
J1 J4 : USB Port Connector
PJ2 J2
J5 J7 J4 J8
J6 J5 : USB Port Connector
PJ1
J6 : Inverter Board Connector
J7 : USB Port Connector
J8 : USB Port Connector
PJ1 : D/D Connector
PJ2 : MISC Connector
SW1 : Cover Switch
97
SW1 SW2 SW3 SW4 SW5 SW6 J501 : Easy Start Button Connector
SW1 : Programmable Easy Start Button Switch
SW2 : Programmable Easy Start Button Switch
SW3 : Programmable Easy Start Button Switch
SW4 : Programmable Easy Start Button Switch
J501 SW5 : Programmable Easy Start Button Switch
SW6 : Programmable Easy Start Button Power Switch
98
99
U6
100
PU508
PU510
PU511
U6 U5 U3
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
TRC Interface
Name Pin Attr Signal Description
BATOK I Battery Power OK:
3.3V -RTC When the internal RTC is enabled, this signal is used to indicate
that the power of RTC well is stable. It is also used to reset the USB Interface
logic in RTC well. If the internal RTC is disabled, this pin Name Pin Attr Signal Description
should be tied low.
OSC32KHI I RTC 32.768 KHz Input: USBCLK48M I USB 48 MHz clock input:
3.3V-RTC When internal RTC is enabled, this pin provides the 32.768 3.3V/5V -M This signal provides the fundamental clock for the USB
KHz clock signal from external crystal or oscillator. Controller.
OSC32KHO O RTC 32.768 KHz Output: OC[0:5]# I/O USB Port 0-5 Overcurrent Detection:
<3.3V -RTC When internal RTC is enabled, this pin should be connected 3.3V/5V - AUX OC[0:5]# are used to detect the overcurrent condition of USB
with the other end of the 32.768 KHz crystal or left unconnected Ports 0-5.
if an external oscillator is used. UV[2:0]+, I/O USB Port [2:0] Differential:
PWROK I Main Power OK: UV[2:0]- 3.3V - AUX These differential pairs are used to transmit Data/Address
3.3V-RTC A high-level input to this signal indicates the power being /Command signals for ports 0-2. (USB controller 1)
supplied to the system is in stable operating state. During the UV[5:3]+, I/O USB Port [5:3] Differential:
period of PWROK being low, PCIRST# will all be asserted UV[5:3]- 3.3V - AUX These differential pairs are used to transmit Data/Address/
until after PWROK goes high for 12 ms. Command signals for ports 3-5. (USB controller 2)
116
117
118
119
120
121
122
123
125
126
127
128
U504
LCD PANEL
TV-Encoder
SiS301LV/ U4
J509 TV S-VIDEO CH7019
MINI PCI IGUI Host/Memory
200 pin DDR SO-DIMM Socket * 2
Socket Controller
CRT
SiS650
PCI BUS Hyperzip Data Bus
U6 Internal Microphone
HDD
PCMCIA U14 AC Link U15 U16
Controller CDROM Internal Speaker
PCI 1410
MuTIOL Media I/O Audio Codec Amplifier
SPDIF JACK
Cover Switch Controller
J18
U5 SiS961 RJ-11 Jack
U505 M.D.C
RJ-45 Jack
LAN PHY
Power
Switch
LPC FAN
U18
ISA BUS U509
IEEE 1394 IR Module U511 Power Button
Controller Super I/O Micro
PCMCIA/ uPD72872 Print Port Controller
CARDBUS
PC87393
U10 Touch Pad
Socket H8/F3437
Flash ROM
Keyboard
129
Each time the computer is turned on, the system bios runs a series of internal checks on the hardware.
This power-on self test (post) allows the computer to detect problems as early as the power-on stage. Error
messages of post can alert you to the problems of your computer.
If an error is detected during these tests, you will see an error message displayed on the screen. If the
error occurs before the display is initialized,then the screen cannot display the error message. Error codes or
system beeps are used to identify a post error that occurs when the screen is not available.
The value for the diagnostic port (378H) is written at the beginning of the test. Therefore, if the test
failed, the user can determine where the problem occurred by reading the last value written to port 378H by
the 378H port debug board plug at PIO PORT.
130
LED * 8
OR
PIO CONNECTOR * 1
P/N:411904800001
Description: PWA; PWA-378Port Debug BD
Note: Order it from MIC/TSSC
7.3.2 Circuit:
PIO 25 14
PIN{9:2}: PD{7:0}
133
8.1 No Power
8.2 No Display
134
No power
Is the
notebook connected No Connect AC adaptor
to power (either AC adaptor Check following parts and signals:
or battery)? or battery.
Parts: Signals:
Board-level Where from J2 PD506 ADINP
Try another known good power source problem AC PF501 PD504
Troubleshooting ALWAYS
battery or AC adapter.
(first use AC to PL508 +DVMAIN
power it)? PL501 +VDD5S
JS501
No PU502
Power
PD502
OK? Battery PD514
PD505
Yes
Is
the M/B and charger
Replace the BD connected Check following parts and signals:
faulty AC properly? Replace
adaptor or Motherboard
Battery. Parts: Signals:
P15
L32
P25 BATT MIIAVDD
Main Voltage Map U512
P16
PD3,PL5,PQ1,PL6,PU9 +1.8V NOTE:
Charge
P16
U523
USBVDD P1 P3 : Page 1, 2, 3 on D/D board
PU513
circuit diagram.
Discharge PU10
P23
P27 J7 1.25V P6 P29 : Page 6~29 on M/B board
P29
circuit diagram.
L543
P2 PJ2 +PHYVDD
PF501 : Through by part PF501.
P29
L544
PF501 +PHYAVDD
PL501 PD514 PU2
PL508 JO502 PD505 PL504 PU3 JO506
P1 P1 P2
JS501 PU502 PD506 PL505 PU4 JO507 PU503
POWER IN ADINP +DVMAIN +DVMAIN1 +3V_P +3V +3VS To next page
PU4
P2 P2
J2 P2 PU5
PU6 JO1 JS4
P1 P1 P2 P17
PD503 PL3 JO2 PU501 JS5
+5V_P +5V +5VS +5VS_HDD
PD504
P2 JS6 P17
Discharge U3 JS7
P2 ALWAYS USB0VCC5 +5VS_CD
P3 P18
U1 U505
USB5VCC5 VCCA
P2 PJ2
JS2 P20 P18
JS3 U505
PU4 5V_AMP VCCP
P27
J7 PU5
PU6 JS505
P20
F504 PL3 P1 P1 P2 L554
U506 PU507 JO505 PQ1 AVDDAD
+12V_P +12V +12VS
P27
Q509 P22 P27 JO503 P1 P27 PL7 PU7 JO501
P24 P24
L512 Q8 JO504 PJ1/J4 PU510 PU507 JO502
P27 H8_AVREF1 +5VA +5VAS +D/VMAIN VMAIN +1.8V_P +1.8VS To next page
136
P2 P11 P24 P7
L23 R613
+3VS VDDA48 +2.5V_DDR DDRVREFA
From last page P9 From last page P7
P6 P11
L14 L519 L19 R616
CPUAVDD +DVDD VDDZ DDRVREFB
P6 P9 P11 P11
L15 L10 L18 L22
PHYAVDD +VDDV VDDCPU CBVDDA
P6 P9 P11
L507 L7 L21
P11 L24
AGPAVDD1 +TVPLL_VCC VDDAGP CBVDD
P6 P9 P11 P12
L511 L9 L20 R95
AGPAVDD2 +TVPLL_VDD VDDPCI +DDRVREF
P6 P9 P11
R62 L510 L17
AGPVREF +LVDD0/1 VDDREF
P7 P9 P11 P24 P7
L13 L509 L16 R557
SDAVDD +LVDD2 VDDSD +1.8VS ZVREF
From last page P7
P7 P7 P14
L516 L508 L517 L518
DDRAVDD +LVDD3 SZ1XAVDD VDDZCMP
P7 P9 P14 P7
L505 L512 L26 L514
DCLKAVDD +DAV_VDD SZ4XAVDD DACAVDD1,2
P7 P9 P19 P14
L506 L513 L8 L524
ECLKAVDD +LPLL_VDD +3V_LAN SVDDZCMP
Q503
P7 F503 P10 P14
20
L515 L504 Q529 L38
Z1XAVDD LCDVCC +3VS_SPD IDEAVDD
P7 P11 P14
L12 L520 R109
Z4XAVDD VDDA SZVREF
137
PL501
PF501 8
J2 120Z/100M
JS501 3 7 PD505
2 6
POWER IN 1
D
5 +DVMAIN
S
PU502 PD506
G
PR508
100K
PQ501
2N7002 LEARNING 81
P22
Step1 : Connect Adaptor to ( D/D BD ) J2 & O/P “ALWAYS”. 45
U509
P2 P27
Step2 : “ALWAYS” --> U506 Generate +5VA. PR509
1M
Micro
PJ2 J7
Controller
Step3 : H8 O/P “LEARNING” for Charger Circuitry. PR3 R674
10 2.2K H8/F3437
3 6 I_LIMT 39
Step4 : For MOSFET “PU502” G=0,D<-->S. +VDD5S VCC PU1 OUT 47
1
PC5
PC4 4,5 P2
Step5 : O/P “ADINP”& “+DVMAIN”. 0.1µ RS+/- 1µ
MAX4173FEUT-T
R724
100K
-H8_RESET
ALWAYS U506 H8_AVREF1 Q509 +5VA Q511 +5V +5VA
F504 LP2951-02BM SI2301DS SI2301DS
8 1 D S S D
IN OUT
7
F/B
P27 2
D508 D516 C698 C699 R725 RESET
6 2 R621
5VTAP SENSE
G
UDZ5.6B
G
Mother Board
138
+5VAS 4 2
G
0.01µ 10µ 0.01µ 100µ 4.7K 4.7K PD4 100K PR7 100K RLZ20C
EC31QS04 130K 20K
PR3
8
1.25V 3
100K + LI_OVP
PQ3 1
MMBT2222A 2 _ PR16
33k
PU514A
4
4
6
12.40V 0 1 0 0
2
From H8 PQ2B PQ2A From H8
5
1.25V 5 BATT_DEAD
+
PC575 7
0.01µ PC566
1µ 6 _
To H8
PR541 JS1 PU514A
4
100K LMV393M
C898 PR557
PC570 0.1µ
PQ510 100K
0.1µ
SCK431LCSK-5
139
D/D Board
PU513
SI4835DY
8
7 3
BATT1 6 2
BATT 5 1
VMAIN
S
PU512
G
SI4835DY
PC579 PC578
1000P 0.01µ 8
7 3 PR553
6 2 100K
5 1
D
S
G
PR564
301K
+5VA H8_AVREF1
PR552
33K
L521
PL504 -ADEN
120Z/100M
120Z/100M PQ508
J14 2N7002
PR551 C709 C708 C731 C728
PL505 226K 0.1µ 0.1µ 0.1µ 0.1µ
PF502
120Z/100M
P23 1,2 ADINP PQ509
+5VA
DTC144WK
4,9,59 36,37
3
-ADEN 47
PC583 PC584 P22
Battery Connector
3 BAT_T BAT_TEMP 42
Micro
R671 C707
22 68P
PC19 PR12 PR563 PC582 C737 C736 3 Controller
0.1µ 20K 100K 0.1µ 0.1µ 0.1µ
R655 H8/F3437
C710 1M
68P
2
X503
16MHZ
140
No Display
47 R632 22 SDRAMCLK
U4
2 FS0 R630 33 REFCLK0
P11 IGUI
+3VS 44 R635 33 HCLK_SIS650
L520 Host/Memory
300Z/100M HCLK_SIS650#
43 R639 33
36 Controller
R636 R640 FWDSDCLKO SiS650
C715 C719 C718
49.9 49.9
0.1µ 0.1µ 1000P +3VS
To next page
37 R875 R624
10K 4.7K D520
45 CPU_STP#
P14 P15 P16
U508 3 FS1 R633 33 REFCLK1
L17 120Z/100M VDDREF 1 U14
+3VS R625 33 REFCLK3
R660 33
4
3
2
17 CLK_CARDPCI To U6
X502 PCMCIA Controller P18
C701 14.318MHz
10P
1
142
P12 J505
FWDSDCLKO 8 2 R90 0 CLK_DDR0
CLK_INT
From previous page
1 R91 0 CLK_DDR0#
+2.5_DDR
4 R89 0 CLK_DDR1
L22
300Z/100M
CBVDDA 10
VDDA 5 R88 0 CLK_DDR1#
19
C99 C112 C150 C110 FB_OUTT
10µ 0.1µ 0.1µ 0.1µ
R99
22 C196
10P
U27
P12 J506
17 R98 0 CLK_DDR3
Bit 2 Bit 7 Bit 6 Bit 4 Bit 5 CPU SDRAM ZCLK AGP Clock
FS4 FS3 FS2 FS1 FS0 (MHz) (MHz) (MHz) (MHz)
R97 0
0 0 0 0 0 66.7 66.67 66.67 66.67
Buffer 16 CLK8_DDR3#
143
+5VS +5VS
U502
R518 MIC5248 R517
U2 10 10K
+3VS
1,3 4 CPU_CORE_EN
MAX809 IN PG
PWROK
EN P5 VCCPVID
3 2 5
VCC RESET# C514 OUT
0.1µ
C223 P7 R145 C513 P4
0.1µ 100K 1µ
+3V
D513 +VCC_CORE
RLS4148
PWROK U1
P6 P7
CPU
R12 R512
R705
301 51
P24 P26 CPU_CORE_EN 1K
AUXOK U4 CPURST#
Pentium 4
IGUI CPUPWRGD
R706 C782
D15 100K 22µ
PU510 RLS4148 Host/Memory
H_PWRGD
SW502 R718
10K 4 P22 1 -H8_RESET 1 SIS_PWRBTN#
To I/O devices
SiS301LV PCMCIA LPC MINI PCI IEEE 1394
1K
VCC RESET Controller Chrotel/CH7019 Controller Super I/O Socket Controller
3
MN U515 91 SIS_PWRBTN Q515
SiS961
R724 DTC144WK AC97_RST# P19 P20
C799 100K
0.01µ J18 U15
MDC Audio Codec
144
Remove all the I/O device & cable from Replace Parts: Signals:
motherboard except LCD panel or extended Motherboard
U4 R828 +3VS TX2OUT[0:2]+
monitor. U504 R829 LCDVCC TX2OUT[0:2]-
U509 R830 ENAVDD BLADJ
J3 L514 PID[0:2] KH8_ENABKL
J7 L512 TXCLK+ -LID
Connect the I/O device & cable PJ2 L513 TXCLK-
Display Yes to the M/B one at a time to find J6 L515 TX2CLK+
OK? out which part is causing the Q503 SW1 TX2CLK-
problem. F503 R511 TXOUT[0:2]+
L504 TXOUT[0:2]-
No Q2
145
Q2 C506 24 TXCLK+ 8
DTC144TKA R1 0.1µ P9
25 TXCLK- 10
U504
5 TX2CLK+ 7
LCD Connector
ENAVDD 127 6 TX2CLK- 9
SiS301LV/
33,30,27 TXOUT [0:2]+ 20,26,25
DISPLAY LCD_ID2 LCD_ID1 LCD_ID0 ENABKL 128
Chrontel
34,31,28 TXOUT [0:2]- 22,28,27
P7 UNIQAC
HYUNDAI
0
0
0
1
1
0 17,14,11 TX2OUT [0:2]+ 13,14,19
LCD
HANNSTAR 0 1 1 CH7019
CMO 1 0 0 18,15,12 TX2OUT [0:2]- 15,16,21
U4
R828 0 LCD_ID0
IGUI PID0 31
R829 0 LCD_ID1
Host/Memory PID1 33
R830 0 LCD_ID2
Controller PID2 35
1 X
4
3
2
RP40
SiS650 R74
10K*4
100
DC Power Board
5
6
X 8
7
+5VA J6
L514 2,3
+5V
P27 J7 PJ2 P2
R642 L512 11
P2
10K +5VS
P22
U509 45 BLADJ BLADJ L513 4
Inverter
146
No
Display Yes
Replace faulty monitor.
OK?
One of the following parts on the mother-board may be
defective, use an oscilloscope to check the following signal or
No
replace the parts one at a time and test after each replacement.
Remove all the I/O device & cable from Replace Parts: Signals:
motherboard except monitor. Motherboard
U4 Q505 CRT_IN#
U14 Q502 REFCLK0
U508 Q501 CRT_DDDA
J2 Q506 CRT_HSYNC
Connect the I/O device & cable R1 FA501
Yes CRT_VSYNC
Display to the M/B one at a time to find R566 L503
R546 L502 CRT_DDCK
OK? out which part is causing the R547 CRT_RED
L501
problem. R548 CRT_GREEN
No CRT_BLUE
147
+3VS
+3VS
R2 J2
R1
+3VS P15 1K
1K
REFCLK0 CRT_IN#
5
P11 To U14 SiS961
From U508 Clock Gen.
C1
R552
2.2K
R558
2.2K
FA501 1000P P10
G 120OHM/100MHZ
R566
100 CRT_DDDA S D 12
G Q505
P7 R546 2N7002
33 CRT_HSYNC S D 13
G Q502
Controller
1X
X
6,7,8,10
3
2
2
4
2
4
3
C600
VVBWN 0.1µ
RP502 CP501 CP502
SiS650 C593
+1.8VS
75*4 22P*4 22P*4 JL1
VCOMP 0.1µ
L514
6
7
7
5
7
5
6
120Z/100M JL501
X
DACAVDD1,2
R545
130
VRSET
148
149
+3VS
L516 +1.25V
120Z/100M
DDRAVDD
RP7
SMBCLK P12
470
CKE [0:3] CKE 0,1
+2.5V_DDR
P7 DDR_DQM [0:7] DQM [0:7]
+DDRREF
DDR_MD [0:63] MD [0:63]
DDR SODIMM
DDR_BA [0,1], DDR_CS [0:3]# BA [0,1], CS [0:3]# CS [0,1]#
U4
R90,R89,R94
RP8~RP12 10*8 +3VS R91,R88,R93
+2.5V_DDR RP13~RP15 0*8 0 CLK_DDR [0:2] , CLK_DDR [0:2]#
RP16~RP20 10*8
IGUI P15
C689 R613 R836 R837
Host/Memory 0.01µ 150 From U14 SiS961 4.7K 4.7K J506
DDRVREFA
SMBDATA
Controller
C688 R612 +2.5V_DDR
0.01µ 150 SMBCLK
P12
SiS650
C692 R616 R658
0.01µ 150 33
DDRVREFB 47 P11 U508 35
+2.5V_DDR
C693 R615 CS [2,3]#
0.01µ 150 34 +DDRVREF
DDR SODIMM
Clock Gen.
R599
4.7K ICS952001 R662
R95
DRAM_SEL 33
+3VS 1K
R632 7
22
P11 CKE 2,3
SDRAMCLK U9
22 R98,R100,R102 R556
R97,R101,R103 1K
FWDSDCLKO 8 Clock Buffer 0
2,1,4,5,13,14,17,16,24~27 CLK_DDR [0:5] , CLK_DDR [0:5]# CLK_DDR [3:5] , CLK_DDR [3:5]#
R614
ICS93722
22
150
Keyboard or Touch-Pad
Test Error
Check
Yes
U509, J13, J20 Re-soldering
for cold solder?
Is K/B or
T/P cable connected to No
Correct it. Board-level
notebook Troubleshooting
properly? No
151
+5VA H8_AVREF1
L521
120Z/100M
+5VA
+3VS
Internal Keyboard Connector
U11
R245 R138 R125 U509
4.7K 10K 10K
R146
U511 0
Level Shift
72 -ROMCS 8 9 -H8_KBCS 95
F1 J20
0.25A
LPC Micro KO 0,1 5,6
R690
Controller +5V
Super I/O 73 -MCCS
0
14 15 -H8_MCCS 98 KI 0,5 7,8
P21
152
153
+5VS
+5VS JS4 +5VS_HDD
R214 J19
10K
JS5
41, 42
R215
C261 C273 C258
10K
0.1µ 4.7µ 0.1µ P17
R1 Q18
DTC144TKA
+5VS D19
R200
470 PG1102W
39
+5VS
R144
P14 4.7K
RP42, PR45
U14 10*8
IDE_PDD[0:15] PDD[0:15] 2~18
154
CD-ROM Driver
Test Error
Test Yes
Replace the faulty parts. Parts: Signals:
OK?
U14 R208 +5VS
No J12 R176 +5VS_CD
R215 R203 -PCIRST
Q19 R170 IDE_SIORDY
Check the CD-ROM driver for proper Replace Q18 R207 IDE_SDD[0:15]
Motherboard R214 IDE_SDA[0:2]
installation. R777
JS6 IDE_SDCS3#
JS7 IDE_SDCS1#
R204 IDE_SDIOR#
RP41 IDE_SDIOW#
RP44 IDE_SDDACK#
Re - Test Yes
End RP43 IDE_SDDREQ
OK? IDE_IRQ15
No
155
+5VS
+5VS JS6 +5VS_CD
R214 J12
10K
JS7
38~42
R215
C648 C74 C643
10K
4.7µ 0.1µ 0.1µ P17
R1 Q18
DTC144TKA
+5VS D18
R743
470 PG1102W
37
+5VS
R73
P14 4.7K
RP41, PR44
U14 10*8
IDE_SDD[0:15] SDD[0:15] 7~21
156
157
USBCLK_SB
From U508 clock generator
DC Power Board
L524
+3V +3V USB0VCC5
120Z/100M
L523
120Z/100M P27 J7 PJ2 P2 D504
BAW56
USBVDD
R516 -USBOC1
10K 2 R506 C506
P16 C744 C745 C743 -USBOC0_1 3 33K 0.1µ
0.1µ 1µ 10µ
1 -USBOC0
USBVSS J5
C534 R518 1
1000P 47K
USB_OC0_1# L509 P2
OC0,1# 50 600Z/100M
USBP0+ 3
USB_OC3_5#
OC3,5# 48 1 2
R147 USBP0- 4 3 2
22
USBP0_P USBP0+
U14 32 R504 R505 4
USBP0_N USBP0- 15K 15K
34
GND
C86 C87 R148
MuTIOL 100P 22P 22
+5V
Media I/O R75 USB0VCC5 GND_USB
22 3 5
Controller USBP1_P USBP1+ VIN0 P2 VOUT1
L516
26
120Z/100M
USBP1_N USBP1-
4 1
28 VIN1 U3 VOUT0
SiS961 C122 C121 R158
22 C8 C10
100P 22P R3 C517
1µ 1µ
33K 0.1µ
-USBOC1
R142
J7
C9 R5 1
22
USBP3_P USBP3+ 1000P 47K
14
L518 P2
USBP3_N USBP3-
16 600Z/100M
USBP1+ 3
C83 C84 R143 1 2
100P 22P 22
R161 USBP1- 4 3 2
22
USBP5_P USBP5+
1 R508 R509 4
15K 15K
USBP5_N USBP5- JO512
3
GND
C126 C125 R163
100P 22P 22
GND_USB
158
USBCLK_SB
From U508 clock generator
DC Power Board
L520
+3V +3V USB5VC5 120Z/100M
L523
120Z/100M P27 J7 PJ2 P2 D3
BAW56
USBVDD
R10 -USBOC3
10K 2 R7 C525
-USBOC3_5 3 33K 0.1µ
C744 C745 C743
P16 0.1µ 1µ 10µ
1 -USBOC5
USBVSS J8
C11 R8 1
1000P 47K
USB_OC0_1# L522 P3
OC0,1# 50 600Z/100M
USBP5+ 3
USB_OC3_5#
OC3,5# 48 1 2
R147 USBP5- 4 3 2
22
U14 USBP0_P USBP0+
32 R513 R514 4
15K 15K
USBP0_N USBP0-
34
GND
MuTIOL C86 C87 R148
22
100P 22P +5V
Media I/O
R75 USB5VCC5 GND_USB
3 5
Controller USBP1_P
22
USBP1+ VIN0 P3 VOUT1
L504
26
120Z/100M
USBP1_N USBP1- 4 1
28 VIN1 U1 VOUT0
SiS961 C122 C121 R158
22 C3 C509
100P 22P R2 C504
1µ 1µ
33K 0.1µ
-USBOC3
R142 J4
22 C1 R4
USBP3_P USBP3+ 1
14 1000P 47K
USBP3_N USBP3- L508 P3
16
600Z/100M
C83 C84 R143 USBP3+ 3
100P 22P 22 1 2
R161 USBP3- 4 3 2
22
USBP5_P USBP5+
1
R503 R502 4
USBP5_N USBP5- 15K 15K
3 JO501
C126 C125 R163 GND
100P 22P 22
GND_USB
159
No
160
+5VS
P3 U501
D501
PAC128401Q BAS32L
PJ2 P2 RP1 12 13
J3
0*4
Mother Board P27 J7 -P_STB 8 1 -PP_STB 11 14 STB# 1
25
-P_AFD 7 2 -PP_AFD 10 15 AFD# 14
P3
23
P_LPD0 6 3 P_LPD0 9 16 LPD0 2
43
RP501 -P_ERR 5 4 -PP_ERR 8 17 ERR# 15
0*4 21
P_LPD [0:3] DP_LPD [0:3] P_LPD1 RP2 8 1 PP_LPD1 7 18 LPD1 3
41
0*4
-P_INIT -PP_INIT
P21 RP503 19
7 2 6 19 INIT# 16
RP505 P3
LPC -P_INIT, -P_SLIN
0*4
-DP_INIT, -DP_SLIN U502
-P_ACK, P_BUSY -DP_ACK, DP_BUSY PAC128401Q GND_IO2
Super I/O RP3 12 13
0*4
R501 P_LPD4 8 1 PP_LPD4 LPD4 6
35 11 14
PC87393 0
P_PE DP_PE P_LPD5 PP_LPD5
7 2 10 15 LPD5 7
33
P_LPD6 6 3 PP_LPD6 9 16 LPD6 8
31
P_LPD7 5 4 PP_LPD7 8 17 LPD7 9
CP503 C504 29
VDD[0:3] +3VS 22P*4 22P -P_ACK -PP_ACK
8 1 7 18 ACK# 10
36
P_BUSY 7 2 PP_BUSY 6 19 BUSY 11
34
P_PE 6 3 PP_PE 5 20 PE 12
32
CP504 CP505 CP506
22P*4 22P*4 22P*4 P_SLCT 5 4 PP_SLCT 4 21 SLCT 13
27
RP4 3 22
X X
0*4 2 23
1 24
GND_IO2 GND_IO2
161
Audio Failure
No
162
L532
600Z/100M J21
AUDIO IN L553
120Z/100M
AVDDAD 1
Internal
1,9 R728 R727
+3VS DVDD1,2 2.7K MIC_VREF 2.2K 2 MIC
C88 C116 C118
10µ 0.1µ 47P
C801 C788 R739
1µ 2.2µ 2.7K
+5VS AVDDAD J28
L554 3
JS505 120Z/100M
25,38 5
AVDD1,2 C272 L531
600Z/100M MIC_3 4
1µ
C784 C117 C120 21 MIC1 MIC MIC_2 2
10µ 0.1µ 0.1µ
1
C798 L535
P20 C264 220P 600Z/100M External
0.1µ
R154
22
22 MIC2 MIC
AC97_SDIN 8
P15 AC97_SDOUT 5
C271 R187
AC97_SYNC R764 22 10 1µ 6.8K
20 CDROM_RIGHT 2
U14 U15
AC97_RST# 11 C269 R185 P17 J12
1µ 6.8K
18 CDROM_LEFT 1
AC97_BITCLK R699 22 6
MuTIOL C270 R186 CDROM
Audio Codec 19 1µ 6.8K CONN
Media I/O CDROM_COMM 3
SPK_OFF#
Controller To next page C227
ALC201 R193 R191 R192 R141
10P
2 100K 100K 100K 0
SiS961 X3 R150
24.576MHZ 1M C274 R173
0.1µ 0
SB_SPKR LINE/IN/L 23
AVDDAD 3
L40 120Z/100M
L545 120Z/100M
5
48 SPDIFOUT
R697 C777
1 470K 0.1µ L546 120Z/100M
4 12
-CARDSPK PC_BEEP
P18 U6 2 36 AOUT_R
L547 120Z/100M
To next page
U513 R698
3
R700 35 AOUT_L
20K
PCI1410GU 10K AGND
163
AOUT_R
0.1µ
4 7 5V_AMP 10 SPKLOUT- 2 L SPK_OFF
Q528 R1 -DECT_HP/OPT
6 L45
From last page U16 600Z/100M J23 DTC144TKA
1 3 R159 From last page
47K R168
AOUT_L 100K
5V_AMP
14
SE/BTL#
2
164
1.Check if the driver is installed properly. Check the following parts for cold solder or one of the following
2.Check if the notebook connect with the parts on the mother-board may be defective, use an oscilloscope
LAN properly. to check the following signal or replace the parts one at a time and
test after each replacement.
Board-level
Troubleshooting Parts: Signals:
No
165
+3V +3V_LAN
L5
120Z/100M +3V_LAN +3V
MIIAVDD 7,8,15,16,25,54,63
VDD[0:6] L8
37 R609 0 120Z/100M
C232 C230 C754 VDD_IO0
0.01µ 0.1µ 10µ +3V_LAN 51 R66 0
JL522 VDD_IO1
MIIAVSS
R595 10K R61 10K C44 C45 C48 C62 C59 C64
55
P0AC 0.1µ 0.1µ 0.1µ 0.1µ 0.1µ 0.1µ
R64
1.5K 18 R49 22K
RESETN
R171 33 LAN_DATAIO 30 C57
1µ C54
R177 33 LAN_DCLK 31 0.1µ
P15 P16 P19
C41
R166 33 LAN_MTXD0 45 10P
R41 R46
R167 33 LAN_MTXD1 46 56 56
R172 33 LAN_MTXD2 47 L6
J9
14 RXIN+ 1
RD+
R178 33 LAN_MTXD3 48 2 1 16 PJRX+ 6
3 RX+
RDC
15 3
U14 LAN_MTXE U5 13 RXIN- 3 4 2
RD-
RX-
PJRX-
P19
43
P19 10 PJTX+ 8
TX+
LAN_MTXC R72 22 44 C310
0.1µ 9 PJTX- 7
MuTIOL TX-
LAN_GND GND_45
166
167
R249
10K +5VS
+3VS SUSPEND# +3VS +12VS
VCCA VPPA
R785
0
J11
3,4 5,6 9
AUX_VCC
-VCCEN0 1 11~13 17,51
PCI_VCC[0:3] -VCCEN1 2 10 18,52
CORE_VCC[0:5] U505
VPPEN0 15
VCCA SKT_VCC0,1
VPPEN1 14 TPS2211 C684
0.1µ
C662
0.1µ
C650
0.1µ
C661
0.1µ
P18
C203
+3VS 0.1µ
P18
R223
10K C217
U513
-CARD_RI 0.1µ CAD[0:31]
To H8 Q20
DTC144WK PCMCIA CAD9 R219 0
-CCBE[0:3]
PCI_AD[0:31]
P14 P15 R789
PCI1410 -CFRAME, -CIRDY, -CTRDY
PCI_AD20 100
IDSEL -CDEVSEL, -CSTOP, CPAR
U14
PCI_C/BE#[0:3]
-CPERR, -CBLOCK, CVS1,2
-CGNT
SiS961 -PCIRST, PCI_GNT0#
R793
0 CCLK R218 0
PCI_INTB#
168
IEEE1394 Fail
169
+3VS
+3VS +PHYVDD
116 SDATA 5
C857 C231 C859 C233
4.7µ 0.1µ 0.1µ 0.1µ 117 SCLK 6
U7
P29
7
+3VS +PHYAVDD NM24C02N
8
87 R242
L544 0 C93
88 R225 1M 0.1µ
U18
C861 C235 C863 C239 C241 C252
4.7µ 0.1µ 0.1µ 0.1µ 0.1µ 0.1µ 1 3
2
4
IEEE 1394 C299
22P
X6
C300
22P
24.576MHZ
CLK_1394PCI
Controller
6
1394 Socket
PCI_C/BE#[0:3]
98 TPB- R195 0 1
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
72
8%104%0
72
8%104%0
72
8%104%0
72
8%104%0
72
8%104%0
721
8%104%0
5 5 5 5
3
5%67
3
5%67
3
5%67
3
5%67
9%
9% 9%1 9%
98%38:7; 98%38:7; 98%38:7; 98%38:7;
1
3
5%67
3
5%67
3
5%67
3
5%67
3
5%67
9% 9%1 9% 9%
98%38:7; 98%38:7; 98%38:7; 98%38:7;
!"#!
3
5%67
3
5%67
3
5%67
3
5%67
3
5%67
+# !"#!
1
3
5%67
3
5%67
3
5%67
3
5%67
3
5%67
3
5%67
3
5%67
3
5%67
3
5%67
3
5%67
1
1
1
- /12
*($%32$)-$
72
,2
*-&4)-&433$%
72 8%04%0
8%04%0
1
1
1
72
%&
,,
8%04%
1
8%04%0
1
1
72 72
8%04%0 8%04%0
1
1
72
8% 04%0
/ /1 /0
2)%
$
*$(%32$)--
034) 034) 034)
1 1 1
)2%&4$(
/1 /1 /1
+1.8VS +1.8V O X X X
,
*
)-$(&&(.
+1.8V +1.8V O O X X 1 COMP
$$$7
3 IN-1
6 SOLDER
+3VA +3.3V O O O 0
+5VS +5V O X X X
+5V +5V O O X X
+5VA O O 0 0
+12VS +12V O X X X
+12V +12V O O X X
!"#
!$ %&'(" +
)(*
%", -" &.
$
+,
&%!'
$
$$
#%
*'
TV
TV
SiS301LV HOST
/CH7019
AGP
DDR SDRAM PC2100
Pannel LVDS
128-pin LQFP
5EI$# Memory Bus / 266MHz
DDR
,20 -
(&'22)'
(&'22)' CRT 702-Balls BGA
()
5#
Local
Memory
Hyper Zip
HyperZip
Data Bus 266MHz
512MB/sec
HUB[0..11]
FOUR USB
LAN PHY
+
MII
/01 10/100 M
HyperZip
ICS1893 LAN
PCI
USB
%&'#
Ultra DMA 33/66/100
5E5'$
IDE
AC'97
/ -'*$. +
$+ +
Ultra DMA 33/66/100
371-Balls BGA
"-
&43)
-
3
!
!"#
-1
&-( "#$
&"''
(-3#
/0
($)
(
2+0 ($) (
!"#
<
7=;%827
!$ %&'(" +
)(*
%", -" &.
1
-POWERBTN
2 3
-SUSB
SW_+5VA S3AUXSW#
SIS_PWRBTN
PSON#
-SUSC
SIS_PWRBTN#
ALWAYS H8_AVREF1 +5VA
H8_PWRON
BATOK
PSON
3 2 AUXOK
+5V +5VS
5
PSON
+12V +12VS PWROK
PSON
4
+3V +3VS
PWR_ON
6
PSON
CPUPWRGD
AUXOK
"#$"%#&
+1.8VS
+5VS
VMAIN
PWR_ON
+2.5V_DDR
+5VS
-SUSC
LEARNING
4 +VCC_CORE
CPU_CORE_EN
H_PWRGD
+VCC_RTC RTC BAT
+5VAS +VCC_RTC
'() !
"#$"%#& "#$"%#&
BATOK
!"#
5
=;%827
!$ %&'(" +
)(*
%", -" 1 &.
51 5
5
%@B001C
%@B001C
@B1001C 3= 3
@B1001C 3
%@1
%@1
;653 5
71
;653 9 %
@1
6%@
%@1 %@1 %@1
%@11
;653@ =; =
5
; 2 ;1 ) 91 %
/ 6
5
PRECISION FSB COMPENSATION RESISTORS 8% 8%6
8% 8%6
8% 1 8%6
675 8%1 8%16
0 1 F
D 1 1 1 8% 8% 6
675 1
0 1 :
785 8%B00 C
D : 65 8%B00 C / 6
68)8@
REQUEST NEW PART NUMBER FOR 51.1 Ohm, 1% resistors required) 1 1 1
0; 1
1 1 1 1 1 1 1 1 1 1
D
/ 6
65
856%
CPU DEBUG PORT 53@
6%=@
7
6
@
/ 6
8567
1 :
6=75685
:
6=75685
1 1 1 1 1 :
6=75685
6%=@ :
6=57 65%<
1
:
6=75685 1 7
6
@ :
6=5765
A
5
8 :
6=5765
A 856;
8
8 :
6=57 65%< 856%8
8 1
8 :
6=57 65%< 8567
8
8 :
6=5765
A :856
1
81 1
:
6=75685
:
6=75685
53@
856;
856;
1
856; D
;F
856%8 856; 856;@
65
856;@ 856%
1
1 2)%
5
8
%49740774
4)
8
8 5
%
1
8 :856 E::
8
2)%
;F 1
1
/1
1
1.5" MAX. / 6
/ 6
51
;F
/ 6
PLACE AT CPU END
11
62
961 536
7%
0 1
D 1
1 1
D /1 %%
4) 2)%
57 :
76
1
69
@ %71
1 1 03
/ 6
PLACE AT CPU END 56 5352% 1
+
1 D
5362
9 113
6=@
0 1
D 53@
1 1
CPU SIGNAL TERMINATION
865
+
D
113
CP1812_7243 SHAPE
GTL Reference CKT
PLL SUPPLY FILTER !"#
5
)837 >4?
!$ %&'(" +
)(*
%", -" &.
/ 6
/ 6
/ 6
%
%1
%
%
%
=
=1
=
=
=
9
91
9
9
9
9
%
%
=
=
%
%1
%
%
%
9
9
9
=
=1
=
=
=
9
91
9
9
9
3%
%
%
=
=
9
)
3 3 3 3 3
)1
+ 3 + 3
)
3 3 3 3 1 1 1 1
)
5 %
/ 6
5 %
5 %
5 % 3 3 3 3 3
%
%
%1
1 % 1 1 1 1 1 1
03 03 03 03 03 03 03 03 03 03
1 1 1 1 1 1 1 1 1 1
1
1
3
3
3 =
3
2 1
1
Place these caps at
CPU north side / 6
; %
;1 %
;
; 11
1 3 3 3 3
3 3 3 3
=
1 =
7 =
7 =
= 1 1
7 = 3 3 3 3 3 1 1 1
7 = 3 3 3 3 3
=1
=
=
1
1 3 3 3 3 3 1
1 3 3 3 3 3
1
9
9
9 <
9 <
9 <
9 <
9
9
9
9
2
21
/ /
2
1
9
9
9
9
9
%
%
%
%
%
%
1
9
9
9
9
=
=
=
=
=
=1
=
1
1
%
%
%
%1
%
=
=
1
3
536
6
)
8) 52 536
6
)
1
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