ALU Codificator 8 biti

module ALU ( A, B, Cin, M, F, O, Cout, egal ); module codif_8_biti ( I, C );

input [3:0] A, B, F; input [7:0] I;

input Cin, M; output reg [2:0] C;

output reg [3:0] O; integer j;

output reg egal, Cout; always @(*) begin

always @(*) begin for ( j = 0; j <= 7; j = j + 1 ) begin

if ( M == 1) if ( I[j] == 1 )

case ( F ) C = j;

0:f=a&b; end

1:f=a|b; end

2:f=a^b;//xor endmodule

3:f=~(a^b);//xnor module test_codif_8_biti;

endcase reg [7:0] I;

else case ( {F,Cin} ) wire [2:0] C;

0:{cout,f}=a; integer k;

1:{cout,f}=a+1; codif_8_biti CODIF( I, C );

2:{cout,f}=a+b; initial begin

3:{cout,f}=a+b+1; for( k = 0; k <= 7; k = k + 1 )

4:{cout,f}=a+~b; #10 I = 2**k;

5:{cout,f}=a-b; end

6:{cout,f}=~a+b; endmodule

7:{cout,f}=b-a; Comparator 4 biti

endcase module comparator_4_biti ( A, B, X, Y, Z );

end input [0:3] A, B;

endmodule output reg X, Y, Z;

always @(*) begin

if ( A < B ) begin

X = 1;
 Y = 0; output reg [7:0] Y;

Z = 0; always @ (*) begin

end if ( EN == 1 )

else if ( A == B ) begin Y = 0;

X = 0; else begin

Y = 1; A = 0;

Z = 0; B = 0;

end C = 0;

else begin Y = 0;

X = 0; case ( )

Y = 0; endcase

Z = 1; end

end end

endmodule

end Demultiplexor

endmodule module demultiplexor ( D, E, A, Y );

module test_comparator_4_biti; input E, D;

reg [0:3] A, B; input [2:0] A;

wire X, Y, Z; output reg [0:7] Y;

comparator_4_biti COMP( A, B, X, Y, Z ); always @(*) begin

initial begin Y = 0;

#0 A=2; B=3; if ( E == 0 )

#10 A=1; B=1; Y[A] = D;

#10 A=2; B=0; end

end endmodule

endmodule module test_demultiplexor;

Decodificator 3 biti reg E, D;

module decodif_3_biti ( EN, A, B, C, Y ); reg [2:0] A;

input EN, A, B, C; wire [0:7] Y;

 integer i; sumator_4_biti SUM( A, B, Cin, S, Cout);

demultiplexor DMUX ( D, E, A, Y ); initial begin

initial begin A = 3; B = 10; Cin = 0;

//Cout=0, S=13 -> 1101
for ( i = 0; i <= 7; i = i + 1 )
#20 A = 7; B = 10; Cin = 0;
#10 A = i;
//Cout=1 -> 10001
end
end
endmodule
endmodule
Sumator 4 biti
Sumator 1 bit
module sumator_4_biti ( A, B, Cin, S, Cout);
module sumator_1_bit ( A, B, Cin, Cout, out);
input Cin;
input A, B, Cin;
input [3:0] A, B;
output Cout, out;
output reg Cout;
assign { Cout, out } = A + B + Cin;
output reg [3:0] S;
endmodule
always @(*) begin
// TESTARE SUMATOR
if ( A + B + Cin <= 15) begin
module test_sumator_1_bit;
Cout = 0;
reg A, B, Cin;
S = A + B + Cin;
wire Cout, out;
end
sumator_1_bit sumator_1( A, B, Cin,
else begin Cout, out);

Cout = 1; initial begin

S = A + B + Cin; #10 A = 0; B = 0; Cin = 0;

end #10 A = 1; B = 0; Cin = 1;

end #10 A = 1; B = 1; Cin = 1;

endmodule end

module test_sumator_4_biti; endmodule

reg Cin; Numărător reversibil

reg [3:0] A, B; module numarator_reversibil (data, up_down,

enable, load, clock, reset, result,
wire Cout; terminal_count);
wire [3:0] S;
 input [3:0] data; module test_numarator_reversibil;

input up_down, enable, load, clock, reg [3:0] data;

reset;
reg up_down, enable, load, clock, reset;
output reg [3:0] result;
wire [3:0] result;
output reg terminal_count;
wire terminal_count;
always @(posedge clock) begin
numarator_reversibil numarator1(data,
if (reset==0) begin up_down, enable, load, clock, reset, result,
terminal_count);
result=0;
initial begin
terminal_count=0;
reset=0;
end
#10 reset=1;
if (load==0)
load=0;
result=data;
data=10;
else if (enable==0)
#10 load=1;
result=result;
enable=1;
else if (up_down==1) begin
up_down=1;
result=result+1;
#150 up_down=0;
if (result==15)
end

terminal_count=1; initial begin

else terminal_count=0; clock=0;

end forever #5 clock=~clock;

else begin end

result=result-1; endmodule

if (result==0) Multiplexor 4 biti

module mux_4_1 ( E, D, S, Y );
terminal_count=1;
input E;
else terminal_count=0;
input [1:0] S;
end
input [3:0] D;
end
output reg Y;
endmodule
 integer i; reg A, B, Sel;

always @(*) begin wire out;

if ( E == 0) multiplexor_2_1 multiplex (out, A, B,

Sel);
for ( i = 0 ; i <= 3 ; i = i +
1) initial begin

Y = D[S]; #10 A = 0; B = 0; Sel = 0;

else Y=0; #10 A = 0; B = 1; Sel = 0;

end #10 A = 1; B = 0; Sel = 1;

endmodule #10 A = 1; B = 1; Sel = 1;

module test_mux_4_1; end

reg E; endmodule

reg [1:0] S; Mux 8.1

reg [3:0] D; module mux8_1 ( IN, SEL, OUT);

wire Y; input [7:0] IN;

mux_4_1 MUX( E, D, S, Y ); input [2:0] SEL;

initial begin output OUT;

#0 E = 1; D = 3; wire y1, y2;

#10 S = 0; E = 0; mux4_1 MUX1 ( IN[3:0], SEL[1:0], out30

);
#10 S = 1;
mux4_1 MUX2 ( IN[7:4], SEL[1:0], out47
#10 S = 2;
);
#10 S = 3;
not not_sel ( n_sel2, SEL[2]);
End endmodule
and AND1 ( y1, out30, n_sel2 );
Multiplexor 2 biti
and AND2 ( y2, out47, SEL[2] );
module multiplexor_2_1 (out, A, B, Sel);
or OR_out ( out, y1, y2 );endmodule
input A, B, Sel;
module test_mux8_1;
output out;
reg [7:0] IN;
assign out = ( Sel == 0) ? A : B;
reg [2:0] SEL;
endmodule
wire OUT;
module test_multiplexor_2_1;
mux8_1 MUX_TEST( IN, SEL, OUT);
 initial begin

IN = 8'b11110000;

SEL = 1;

end

endmodule

RAM

module raam8x3(data,adresa,clk,oe,we,dout);

input [2:0] data,adresa;

input clk,oe,we;

output reg [2:0] dout;

reg [2:0] memorie[7:0];

always@(negedge clk) begin

if(oe==1)

dout=3'bz;

else

if(we==1)

memorie[adresa]=dout;

else

dout=memorie[adresa];

end

endmodule