1798 IEEE TRANSACTIONS ON POWER SYSTEMS, VOL. 21, NO.

4, NOVEMBER 2006

Synchronous Compensators: Models Verified by

Tests of Automatic Voltage Regulator, Reactive
Power Control, and Voltage Joint Control
Jorge Luis Agüero, Senior Member, IEEE, Patricia Liliana Arnera, Senior Member, IEEE,
Raúl E. Bianchi Lastra, Senior Member, IEEE, and Mario César Beroqui

Abstract—This paper presents models verified by tests of the ex-

citation control systems (ECSs) of six large synchronous compen-
+
sators (SCs) rated 125/ 120 MVAr.
These equipments for grid voltage control are placed in the sub-
station Ezeiza of 500 kV belonging to the Interconnected Argentine
System (SADI in Spanish). The substation Ezeiza is located in the
SADI load center.
Each SC has an ECS integrated by an automatic voltage reg-
ulator (AVR) with several limiters and a reactive power control
(RPC). ECSs are governed by a single voltage joint control (VJC)
to control the voltage at a 500-kV bus bar.
The ECS is UNITROL F from ABB and, the VJC is implemented
in a programmable logic controller (PLC).
The AVR, RPC, and VJC models are presented. These models
were predefined with information furnished by the manufacturer.
Then, these models were validated by tests. Test records and
their simulations with the proposed model are also presented. Fig. 1. Substation Ezeiza. SCs plant.
Described models have been incorporated to the database of dy-
namic models used for stability studies in the SADI.
Index Terms—Control system, excitation systems, limiters, mod- and carries power from Comahue electric area, located in the
eling, reactive power control (RPC), testing, voltage control. south SADI.
Comahue has several thermal and hydraulic power plants,
with close to 10 000 MW of generation capability.
I. INTRODUCTION The last two of these six lines are connected to substation

S EVERAL tests were made at synchronous compensators

(SCs) plant during the commissioning of a new excitation
control systems (ECSs). These tests were made to verify all the
models involved and their adjustments.
The SCs are a 3901/01/660 type from General Electric, rated
13.8 kV and 125/ 120 MVAr. Each SC has a shaft mounted
exciter 3901/01/340 type from General Electric used as a driving
motor for startup.
Fig. 1 shows the substation Ezeiza where the SCs are em-
placed. Each pair of SCs is connected to one of the two secon-
daries of a transformer rated 132/13.8/13.8 kV and 250/250/250
MVA with Yd1/Yd1 connection and with individual on-load tap.
Each primary of these three transformers is connected to the ter-
tiary of a transformer rated 500/220/132 kV and 800/800/350
MVA with Yy0/Yd1 connection. The substation Ezeiza is inter-
connected to SADI grid through six 500-kV lines. Four of these
six lines are 1600 km long, with series capacitor compensation,
Manuscript received September 15, 2004; revised December 23, 2004. This
work was supported in part by TRANSNER SA. Paper no. TPWRS-00500-
2004.
The authors are with the IITREE-LAT, Facultad de Ingeniería Universidad
Nacional de La Plata, La Plata, Argentina (e-mail: iitree@iitree-unlp.org.ar).
Digital Object Identifier 10.1109/TPWRS.2006.879253
General Rodríguez, the connection point with the north SADI.
Substation Ezeiza is connected to the SADI load center
(Buenos Aires city and surroundings) through several 220-kV
lines. Then, the SCs plant control the 500-kV voltage at a
critical node of SADI grid.
Each SC has a new ECS integrated by an automatic voltage
regulator (AVR) and a reactive power control (RPC). The AVR
has the following limiters: one over excitation limiter (OEL),
two under excitation limiters (UEL), and a V/Hz limiter. The
AVR also has compensation or droop to control a different
voltage from the measured one.
The new voltage joint control (VJC) is implemented in a PLC.
Fig. 2 shows a simplified model of the six SCs at Ezeiza plant
with the different control loop involved and their interconnec-
tion. Fig. 3 shows a simplified block diagram of one ECS shown
in Fig. 2. This block is the same for each of the six SCs. The VJC
set point (SP) for 500-kV bus voltage is fixed by plant operator.
The VJC block generates the set point (QT SP) for each of the
six RPCs with the error between its set point (SP) and its con-
trolled voltage (500 kV). Then, steady-state control of 500-kV
bus voltage is obtained through the VJC operation as a tertiary
closed loop control that changes simultaneously all the RPCs
set points.

0885-8950/$20.00 © 2006 IEEE

AGÜERO et al.: SYNCHRONOUS COMPENSATORS: MODELS VERIFIED BY TESTS 1799

TABLE I
SYNCHRONOUS MACHINE PARAMETERS

Each SC has the following inputs:

• From the AVR: the field voltage (EFD);
• From the grid: the stator or terminal current (IT);
• From prime mover: The mechanical power (MP). MP is
Fig. 2. SCs plant model. Simplified block diagram.
equal to 0 because the SC does not have prime mover.
The ECS (see Fig. 3) is composed by the blocks RPC, AVR,
and AVR limiters.
The RPC block generates the voltage (UT SP) set point for
the AVR with the error between its set point (QT SP) and its
controlled reactive power (QT).
The AVR block generates the control voltage (Out) for the
Rectifier block with the error between the set point (UT SP)
and the measured voltage (500 kV). The measured voltage (500
kV) is internally compensated (negative droop) to control an
intermediate voltage between the stator or terminal voltage (UT)
and the 500-kV bus voltage.
The AVR Limiters block has all the AVR limiters inside.
The inputs of this block are the controlled voltage (500 kV),
the stator or terminal voltage (UT), the AVR set point (UT SP),
the field current (IFD), the active (PT) and reactive (QT) powers,
and the speed (N).
The rectifier block represents the controlled rectifier of the
excitation system and generates the field voltage (EFD).
Fig. 3. ECS. Simplified block diagram.

II. GRID AND SYNCHRONOUS MACHINE MODELS

Each RPC generates the voltage set point (UT SP) for its asso-
ciated AVR, processing the error between the set point (QT SP) A. Synchronous Machine
and the controlled reactive power (QT). Then, the steady-state The SCs were modeled with the IEEE Model 2.2, complete
reactive power is shared between SCs by RPCs operation as a second-order model with logarithmic saturation to represent
secondary closed loop control. synchronous machine [6]. Also, the equation for rotating
Each AVR generates the field voltage (EFD) for its associated masses was modeled. The synchronous machine parameters
SC with the error between its set point (UT SP) and its controlled are shown in Table I (rated 125 MVA and 13.8 kV).
voltage (500 kV) corrected by a droop. Then, AVR operates as
a primary closed loop control. B. Power Grid
Similarly, VJC, RPC, and AVR control systems for a SCs
plant have been reported but with VJC and RPC working in par- Transformers were modeled by their reactances, with the fol-
allel as secondaries closed loop controls, modifying separately lowing values rated at 100 MVA.
AVR set point, [1], [2]. Another control scheme applied to power 500/220/132 kV transformer (T1):
plants, like high side voltage control (HSVC), has been reported • ; and
[3]–[5]. Some of these HSVCs work without direct measure-
ments of controlled high voltage [4], [5]. The high speed of 132/13.8/13.8 kV transformer (T2):
HSVC improves short-term voltage and angle stability. • ; and
Each ECS has the following inputs:
• From the system grid: the internally compensated con- The grid was represented by an infinite bus connected
trolled voltage (500 kV); with a reactance to the 500-kV side of transformer T1.
• From the SC: the stator or terminal voltage (UT), the active For each test simulation, the and values were selected
(PT) and reactive (QT) powers, the speed (N), and the field to obtain the terminal or stator voltage (UT) and the reactive
current (IFD). power (QT) recorded during the test.
1800 IEEE TRANSACTIONS ON POWER SYSTEMS, VOL. 21, NO. 4, NOVEMBER 2006

TABLE II
VJC SETTINGS

III. VJC, RPC, AND AVR MODELS

All models were constructed with information furnished by
manufacturer and according to [7]. All the model variables are
expressed in per unit of the following rated values:
• stator terminal voltage (UT) 13.8 kV;
• stator terminal current (IT) 5.23 kA;
• reactive power (QT) 125 MVAr;
• field voltage (EFD0) 129.5 V;
• field current at air gap line (IFD0) 740 A;
• field current at rated UT and QT (IFDN) 1625 A; Fig. 4. AVR limiters. Block diagram.
• 500-kV bus voltage (500 kV) 500 kV.
Next descriptions of VJC, RPC, and AVR models are in the
form of Laplace transfer function or Laplace block diagram,
although these controls are implemented digitally.

A. Voltage Joint Control (VJC)

The VJC output (QT SP) is sent to each RPC by means of a
4/20-mA transmission current loop. The VJC is a type con-
trol with non-wind-up integral action. The set point (SP) for the
controlled voltage, the 500-kV bus voltage (500 kV), is passed
through maximum and minimum value limiters (SP Max and
SP Min). This limited set point is the input of a ramping block
with fixed slope (SP Slope). The ramping output is the set point
input for the control. The controlled voltage (500 kV) is
measured with a first-order low-pass filter transducer (Tt time
constant). The transducer output is passed through maximum
and minimum value limiters (U Max and U Min). This limited
controlled voltage is subtracted from control set point to
conform the control error (E). Fig. 5. Error limiter. Block diagram.
The control has the following transfer function:

TABLE III
(1) RPC SETTINGS

where is the time constant of integral action, and is the

proportional gain. is the number of SCs in service. The
output of control (QT SP) is limited (QT SP Max and QT
SP Min). The VJC settings are shown in Table II.
B. Reactive Power Control (RPC)
The RPC is a I type control with non-wind-up integral action.
TQ is the time constant of integral action. The reactive power set
point (QT SP) is furnished by the VJC.
The controlled reactive power (QT) is measured by a
first-order low-pass filter transducer (Tt time constant). This
measured reactive power is subtracted from I control set point
to conform the error. The error has a maximum and minimum
value of zero when any OEL or any UEL is active in the AVR.
The active limiter information is given by the logic signals
S-OEL and S_UEL from AVR limiters (see Figs. 3–5).
The limited error is passed through a dead band (DB) with
delay on (Delay On). The output of DB block is the input to the
I control. The output of the I control (UT SP) is limited (UT SP
Max and UT SP Min). This limited output (SP_Lim) is the AVR
set point.
The RPC settings are shown in Table III.
AGÜERO et al.: SYNCHRONOUS COMPENSATORS: MODELS VERIFIED BY TESTS 1801

TABLE IV TABLE V
AVR SETTINGS V/Hz COMPENSATION SETTINGS

TABLE VI
V/Hz LIMITER SETTINGS
C. Automatic Voltage Regulator (AVR)
The AVR output (Out) is generated with the limited error
(E_Lim) from the AVR limiters block (see Figs. 3–5). The AVR
transfer function is
TABLE VII
P/Q LIMITER SETTINGS
(2)

The lead/lag time constants of lead-lag filters are selected by

the logic signals LL1 and LL2 from the error limiter block of V/Hz Limiter: This limiter modifies the compensated set
the AVR limiters block (see Figs. 4 and 5). The AVR out (Out) point (SP_Com) generating a limited set point (SP_Lim) equal
has upper and lower limits ( Up and UP). to
Main disagreements between manufacturer furnished and
test verified models are found in the AVR model. Manufacturer
model changes Lead-Lags, with LL1 and LL2 signals, instead
of described Lead-Lag time constants changing. Also, manu-
facturer furnished model has variable upper and lower output
limits at each Lead-Lag filters instead of the described Up
and Up fixed limits at AVR output. (4)
The AVR settings are shown in Table IV.
where is the speed, is the slope of the V/Hz limiter,
D. AVR Limiters and the maximum voltage at nominal speed. This lim-
Fig. 4 shows the AVR limiters block of Fig. 3. This block has iter has a delay on (Delay on). The output changes linearly from
the following limiter functions: SP_Comp to SP_Lim when limiter sets. The output changes im-
• V/Hz limiter; mediately from SP_Lim to SP_Comp when limiter resets. Be-
• P/Q limiter. UEL; sides, there is an upper absolute limit (U_Max) for the limiter
• Max IFD limiter. OEL; output.
• Min IFD limiter. UEL. The V/Hz limiter settings are shown in Table VI.
Also, the AVR limiters block has the following functions: P/Q Limiter (UEL): The limiter output is given by
compensation and error limiter.
All inputs to the AVR limiters block are physical variables
measured by transducers of first-order low-pass filter type
time constant .
Compensation: This block modifies the AVR set point (UT
SP). with a Look-Up table of (5)
In this way, it is possible to control a voltage different from
the measured voltage (U500 kV). The output of this block is the
where is the modulus of active power, is the reactive
compensated set point (SP_Comp) expressed as
power, is a reactive power set point, is the stator
or terminal voltage, is the time constant of first-order filter,
(3) and is the limiter proportional gain. The look-up table
defines a geometric locus in the P/Q plane (Capability diagram)
for capacitive reactive power. The P/Q limiter settings are shown
where is the active power, is the reactive power, and in Table VII.
and the respective “gains.” Max IFD Limiter (OEL): This limiter has two limiter func-
These “gains” take into account the voltage drop between the tions: the IFD maximum limiter and the IFD thermal limiter.
AVR measured voltage (500 kV) and the voltage effectively con- Each function has an associated set point for the field current:
trolled. The compensation settings are shown in Table V (rated IFD Max for the IFD maximum limiter and IFD Th for the IFD
125 MVA). thermal limiter.
1802 IEEE TRANSACTIONS ON POWER SYSTEMS, VOL. 21, NO. 4, NOVEMBER 2006

TABLE VIII TABLE IX

MAX IFD LIMITER SETTINGS MIN IFD LIMITER COMPENSATION SETTINGS

The output of the IFD maximum limiter is
(6)
where is the proportional gain. In this way, the output of the
IFD maximum limiter is negative when the field current (IFD)
is greater than the limiter set point (IFDMax).
The IFD thermal limiter sets when the field current (IDF) is
greater than the limiter set point (IFDTh) for a longer time than
Th, with Th equal to
(7)
where is equivalent to the energy in the field coil and
the inverse of the equivalent thermal time constant with the
field coil warm.
When IFD thermal limiter is set, its output changes from
(8)
to
positive when the field current (IFD) is smaller than the limiter
set point (IFDMin).
The Min IFD limiter settings are shown in Table IX.
Error Limiter: Fig. 5 shows a detail of error limiter block of
Fig. 4. Its inputs are all limiter outputs (OEL and UEL) together
with the error conformed by the error between the limited set
point (Lim_SP) and the controlled voltage (500 kV).
The UEL outputs (IFDMin_Lim and P/Q Lim) and the previ-
ously conformed error are passed by a high value gate (HVG).
The HVG output and the OEL output (IFDMax_Lim) are passed
by a low value gate (LVG).
The output of the LVG is the limited error output (E_Lim).
This error is the input of the control of AVR.
The logic signal S_OEL sets when any OEL is operated. The
logic signal S_UEL sets when any UEL is operated.
When any limiter is set, it selects one of the three possible
values of time constants for the two AVR lead-lag filter. This
selection is made by setting the corresponding logic signals LL1
and LL2.
E. Rectifier
The SC excitation is of static inverting type. The controlled
rectifier bridge is fed by an auxiliary transformer connected to
the 500-kV bus. The rectifier transfer function is

(9)
(12)

where is the proportional gain, and the time constant of

smoothing first-order low-pass filter.
The IFD thermal limiter resets when the field current (IDF) is
smaller than the limiter set point (IFDTh) for a longer time than
Tc, with Tc equal to
(10)
where is the inverse of the equivalent thermal time constant
for field coil cooling.
The Max IFD limiter settings are shown in Table VIII.
Min IFD Limiter (UEL): This limiter can be set when large
under excitation condition with high values of terminal voltage
(UT) takes place. Under such condition, P/Q limiter could not
be set (see (5) for QT_SP). This is the reason to have the two
UELs.
This limiter has the following transfer function:
(11)
where is the proportional gain, and is the limiter
set point. In this way, output of the IFD minimum limiter is
where is the rectifier time constant and the equivalent
source resistance of rectifier. The rectifier parameters are KD
p.u./p.u., and Tr .
IV. TESTS RESULTS
Tests made were previously simulated with the models con-
structed with information furnished by manufacturer. Tests were
made to validate these models. These tests are particularly crit-
ical because they must be made with all the SCs in service. Tests
were made according to [8]–[11].
A. Automatic Voltage Regulator (AVR) Tests
Several AVR tests were made with the RPC out of service to
verify the models of AVR, rectifier, and synchronous machine.
Fig. 6 shows records of a positive ceiling test that was made
adding a pulse of 0.15 p.u. and 0.2 s of width to the voltage set
point (UT SP). Fig. 6 shows the measured and simulated AVR
output (Out) and the measured field voltage (EFD) together with
the respective simulations.
Simulations were made in two ways. Simulation 1: with only
the rectifier model, inputting the test record of AVR out (Out) to
rectifier model. Simulation 2: with the interconnected models
AGÜERO et al.: SYNCHRONOUS COMPENSATORS: MODELS VERIFIED BY TESTS
Fig. 6. AVR. Positive ceiling test. Open loop simulation. Lower traces: mea-
sured (gray) and simulated (black) AVR Out [p.u.]. Upper traces: measured
(gray) and simulated 1 and 2 (black) EFD [V].
Fig. 7. AVR. Negative ceiling test. Open loop simulation. Lower traces: mea-
sured (gray) and simulated (black) AVR Out [p.u.]. Upper traces: measured
(gray) and simulated (black) EFD [V].
of AVR and rectifier, inputting to AVR model the test records
of voltage set point (UT SP), voltage (U500 kV), and reactive
power (QT) for compensation calculation.
Fig. 7 shows records of a negative ceiling test that was made
by adding a pulse of 0.20 p.u. and 0.2 s of width to the voltage
set point (UT SP). Fig. 7 shows the measured and simulated
AVR output (Out) and the measured field voltage (EFD) to-
gether with the respective simulations made in the same way
as for test reported in Fig. 6.
Fig. 8 shows records of a small signal test that was made by
adding a pulse of 0.10 p.u. and 0.8 s of width to the voltage
set point (UT SP). Fig. 8(a) shows the measured and simulated
AVR output (Out) and the measured and simulated field voltage
(EFD). Fig. 8(b) shows the measured and simulated terminal
voltage (UT) and the measured and simulated reactive power
(QT).
Simulation was made in closed loop, with the interconnected
models of AVR, rectifier, synchronous machine, and grid. Sim-
1803
Fig. 8(a). AVR. Small signal test. Closed loop simulation. Lower traces: mea-
sured (gray) and simulated (black) AVR Out [p.u.]. Upper traces: measured
(gray) and simulated 1 and 2 (black) EFD [V].
Fig. 8(b). AVR. Small signal test. Closed loop simulation. Lower traces: mea-
sured (gray) and simulated (black) UT [p.u.]. Upper traces: measured (gray) and
simulated (black) QT [p.u.].
ulation was made by inputting the test record of the set point
pulse (UT SP) to the AVR model.
B. AVR Limiters Tests
Several AVR tests were made with the RPC out of service to
verify the models of AVR limiters and the associated logics.
V/Hz Limiter Test: V/Hz Limiter test was made by changing
settings to ; ; and
.
Fig. 9 shows V/Hz limiter test records. The test was made by
adding a pulse of 0.05 p.u. and 20 s of width to the voltage
set point (UT SP). Fig. 9(a) shows the measured and simu-
lated V/Hz limiter output (SP_Lim) and the measured and simu-
lated AVR output (Out). Fig. 9(b) shows the measured terminal
voltage (UT) and the measured reactive power (QT).
Simulation was made in open loop, with the interconnected
models of AVR limiters, AVR, and rectifier. Simulation was
made by inputting to V/Hz limiter model the test records of
1804
Fig. 9(a). AVR. V/Hz limiter test. Open loop simulation. Lower traces: mea-
sured (gray) and simulated (black) V/Hz limiter out [p.u.]. Upper traces: mea-
sured (gray) and simulated (black) AVR out [p.u.].
Fig. 9(b). AVR. V/Hz limiter test. Open loop simulation. Lower trace: mea-
sured (gray) QT [p.u.]. Upper trace: measured (gray) UT [p.u.].
speed (N), terminal or stator voltage (UT), and compensated set
point (SP_Com). Also, test record of 500-kV bus voltage (U500
kV) was the input to limiter error block (see Fig. 4) to conform
error signal for error limiter block (see Fig. 5).
P/Q Limiter Test: P/Q limiter test was made by changing set-
tings to (for all : 0, 0.25, 0.75 and
1.0 p.u.).
Fig. 10 shows P/Q limiter test records. The test was made by
adding a pulse of 0.05 p.u. and 20 s of width to the voltage
set point (UT SP). Fig. 10(a) shows the measured and simulated
P/Q limiter output (P/Q Lim). Fig. 10(b) shows the measured
terminal voltage (UT) and the measured reactive power (QT).
Simulation was made in open loop, with the interconnected
models of AVR limiters, AVR, and rectifier. Simulation was
made by inputting to P/Q limiter model the test records of reac-
tive power (QT) and terminal or stator voltage (UT), assuming
active power (PT) equal to 0. Also, the test records of 500-kV
bus voltage (U500 kV) and limited set point (SP_Lim) were the
IEEE TRANSACTIONS ON POWER SYSTEMS, VOL. 21, NO. 4, NOVEMBER 2006
Fig. 10(a). AVR. P/Q limiter test. Open loop simulation. Lower traces: mea-
sured (gray) and simulated (black) P/Q limiter out [p.u.]. Upper traces: measured
(gray) and simulated (black) AVR out [p.u.].
Fig. 10(b). AVR. P/Q Limiter test. Open loop simulation. Lower trace: mea-
sured (gray) QT [p.u.]. Upper trace: measured (gray) UT [p.u.].
inputs to limiter error block (see Fig. 4) to conform error signal
to error limiter block (see Fig. 5).
Max IFD Limiter Test: Max IFD limiter test was made by
changing settings to ;
(expressed in pu of IFDN).
Fig. 11 shows Max IFD limiter test records. The test was
made by adding a pulse of 0.05 p.u. and 20 s of width to
the voltage set point (UT SP). Fig. 11(a) shows the measured
and simulated Max IFD limiter output (IFDMax_Lim) and the
measured and simulated AVR output (Out). At first, it can be
seen the IFD maximum limiter operation followed by the IFD
thermal operation. Fig. 11(b) shows the measured field current
(IFD) and the measured reactive power (QT).
Simulation was made in open loop, with the interconnected
models of AVR limiters, AVR, and rectifier. Simulation was
made by inputting the test record of field current (IFD) to Max
IFD limiter model, and by inputting test records of 500-kV bus
voltage (U500 kV) and limited set point (SP_Lim) to limiter
AGÜERO et al.: SYNCHRONOUS COMPENSATORS: MODELS VERIFIED BY TESTS
Fig. 11(a). AVR. Max IFD limiter test. Open loop simulation. Lower traces:
measured (gray) and simulated (black) Max IFD limiter [p.u.]. Upper traces:
measured (gray) and simulated (black) AVR out [p.u.].
Fig. 11(b). AVR. Max IFD limiter test. Open loop simulation. Lower trace:
measured (gray) IFD [p.u.]. Upper trace: measured (gray) QT [p.u.].
error block (see Fig. 4) to conform the error signal to error lim-
iter block (see Fig. 5).
Min IFD Limiter Test: Min IFD Limiter test was made by
changing setting to (expressed in p.u. of
IFDN).
Fig. 12 shows Min IFD limiter test records. The test was made
by adding a pulse of 0.05 p.u. and 20 s of width to the voltage
set point (UT SP). Fig. 12(a) shows the measured and simu-
lated Min IFD limiter output (IFDMax_Lim) and the measured
and simulated AVR output (Out). Fig. 12(b) shows the measured
field current (IFD) and the measured reactive power (QT). Sim-
ulation was made in open loop, with the interconnected models
of AVR limiters, AVR, and rectifier. Simulation was made by
inputting to Min IFD limiter model the test record of field cur-
rent (IFD). Also, test records of 500-kV bus voltage (U500 kV)
and limited set point (SP_Lim) were the inputs to limiter error
block (see Fig. 4) to conform error signal to error limiter block
(see Fig. 5).
1805
Fig. 12(a). AVR. Min IFD limiter test. Open loop simulation. Lower traces:
measured (gray) and simulated (black) Min IFD limiter [p.u.]. Upper traces:
measured (gray) and simulated (black) AVR out [p.u.].
Fig. 12(b). AVR. Min IFD limiter test. Open loop simulation. Lower trace:
measured (gray) IFD [p.u.]. Upper trace: measured (gray) QT [p.u.].
C. Reactive Power Control (Q Control) Tests
Several tests were made with the RPC in service to verify the
models of RPC, AVR, and rectifier.
Fig. 13 shows RPC test records. The test was made by adding
a pulse of 0.2 p.u. and 20 s of width to the RPC set point (QT
SP). Fig. 13 shows the measured RPC set point (QT SP) with the
added pulse, the measured reactive power, and the measured and
simulated RPC output (UT SP).
Simulation was made in open loop, with the interconnected
models of RPC, AVR limiters, AVR, and rectifier. Simulation
was made by inputting to RPC model the test records of reactive
power (QT) and RPC set point (QT SP). Also, test records of
500-kV bus voltage (U500 kV) was the input to limiter error
block (see Fig. 4) together with simulated RPC out (UT SP) to
conform the error signal for the error limiter block (see Fig. 5).
Fig. 14 shows RPC test records with the operation of P/Q lim-
iter. Test was made by adding a pulse of 0.2 p.u. and 20 s of
width to the RPC set point (QT SP). Fig. 14 shows the measured
1806
Fig. 13. RPC. Small signal test. Open loop simulation. Lower traces: measured
(gray) and simulated (black) UT SP [p.u.]. Upper traces: measured (black) QT
SP with added pulse [p.u.] and measured (gray) QT) [p.u.].
Fig. 14. RPC. Small signal test with UEL operation. Open loop simulation.
Lower traces: measured (gray) and simulated (black) UT SP [p.u.]. Upper traces:
measured (black) QT SP with added pulse [p.u.] and measured (gray) QT) [p.u.].
RPC set point (QT SP) with the added pulse, the measured re-
active power, and the measured and simulated RPC output (UT
SP). It can be seen that I control does not integrate its error
signal—the RPC output (UT SP) is constant—due to the oper-
ation of S_UEL logic signal that was generated by P/Q limiter
operation. Simulation was made in the same way as for the pre-
vious test.
D. Voltage Joint Control (VJC) Tests
Several tests were made with the six SCs in service and in
joint control to verify the VJC model. Fig. 15 shows VJC test
records. The test was made by adding a pulse of 0.003 p.u.
and 200 s of width to the VJC set point (SP).
Fig. 15 shows the measured VJC set point (SP) with the added
pulse, the measured 500-kV bus voltage (U500 kV), and the
measured and simulated VJC output (QT SP). Simulation was
made in open loop, by inputting to VJC model the test records of
IEEE TRANSACTIONS ON POWER SYSTEMS, VOL. 21, NO. 4, NOVEMBER 2006
Fig. 15. Voltage joint control. Small signal test. Open loop simulation. Lower
traces: measured (gray) and simulated (black) QT SP [p.u.]. Upper traces: mea-
sured (black) SP with added pulse [p.u.] and measured (gray) U500 kV [p.u.].
Fig. 16. Voltage joint control. Out of service of 150-MVAr shunt reactor test.
Open loop simulation. Lower traces: measured (gray) and simulated (black) QT
SP [p.u.]. Upper traces: measured (black) SP and measured (gray) U500 kV
[p.u.].
VJC set point (SP) and 500-kV bus voltage (U500 kV). Fig. 16
shows VJC records for disconnecting a 150-MVAr/500-kV bus
shunt reactor of substation Henderson. Fig. 16 shows the mea-
sured VJC set point (SP)—constant during test—the measured
500-kV bus voltage, (U500 kV) and the measured and simu-
lated VJC output (QT SP). Simulation was made in the same
way as for the previous test. Figs. 15 and 16 show that simula-
tions match the tests and display the effect of the slow integra-
tion of the input error in the VJC output. Also, it can be noted
that there are other equipments in the grid that affect the 500-kV
bus voltage.
V. CONCLUSIONS
The following conclusions can be pointed out.
• The models furnished by manufacturers were valid with
some corrections.
AGÜERO et al.: SYNCHRONOUS COMPENSATORS: MODELS VERIFIED BY TESTS
• The results of several tests made at SC plant were shown.
Tests were made with SCs in service.
• The proposed models reproduce test records with a good
agreement.
• The models of VJC, RPC, AVR, and their limiters were de-
veloped as “user models” for the power system simulation
program PSS/E from PT inc.
• These models with the corresponding modifications were
incorporated to the database for dynamic studies of the Ar-
gentinean grid.
The controls system described, particularly the VJC and the
RPC, will be readjusted in the next work stage. These readjust-
ments are needed to obtain a faster voltage control at 500-kV
bus, like those obtained with an HSVC that additionally im-
proves system voltage stability [2]–[4].
ACKNOWLEDGMENT
The authors would like to thank the personnel of Transener
SA—the SCs plant owner—for their invaluable collaboration.
They also would like to thank Sr. R. Molina from CAMMESA
for his fruitful comments about models.
REFERENCES
[1] D. Brandt, R. Wachal, R. Valiquette, and R. Wierckx, “Closed loop
testing of a joint VAR controller using a digital real-time simulator,”
IEEE Trans. Power Syst., vol. 6, no. 3, pp. 1140–1146, Aug. 1991.
[2] J. B. Davies and L. E. Midford, “High side voltage control at manitoba
hydro,” in Proc. IEEE Power Eng. Soc. Summer Meeting, Panel Session
Power Plant Secondary (High Side) Voltage Control, Seattle, WA, Jul.
16–20, 2000.
[3] S. Koishikawa, S. Osaka, M. Suzuki, T. Michigami, and M. Akimoto,
“Adaptive control of reactive power supply enhancing voltage stability
of a bulk power transmission system and a new scheme of monitor on
voltage security,” CIGRÉ 38/39-01, 1990.
[4] H. Kitamura, M. Shimomura, and J. Paserba, “Improvement of voltage
stability by the advanced high side voltage control regulator,” in Proc.
IEEE Power Eng. Soc. Summer Meeting, Panel Session Power Plant
Secondary Voltage Control, Seattle, WA, Jul. 16–20, 2000.
[5] J. J. Paserba, S. Noguchi, M. Shimomura, and C. W. Taylor, “Improve-
ment in the performance and field verification of an advanced High
Side Voltage Control (HSVC),” in Proc. IX Symp. Specialists Electric
Operational Expansion Planning (IX SEPOPE), Rio de Janeiro, Brazil,
May 23–27, 2004.
[6] Guide for Synchronous Generator Modeling Practices in Stability
Analyses, IEEE Std. 1110, 1991.
[7] IEEE Recommended Practice for Excitation System Models for Power
System Stability Studies, IEEE Std. 421.5, 1992.
[8] IEEE Guide for Identification, Testing, and Evaluation of the Dynamic
Performance of Excitation Control Systems, IEEE Std. 421.2, 1990.
[9] IEEE Guide: Test Procedures for Synchronous Machines. Part II—Test
Procedure and Parameter Determination for Dynamic Analysis, IEEE
Std. 115-1995.
[10] F. P. de Mello and J. R. Ribeiro, “Derivation of synchronous machine
parameters from test,” IEEE Trans. Power App. Syst., vol. PAS-96, no.
4, pp. 1211–1218, Jul./Aug. 1977.
[11] J. L. Agüero, M. B. Barbieri, and P. L. Arnera, “Ensayo y de-
terminación de parámetros de unidades generadoras del SADI,”
ANDESCOM Congr. IEEE,. Isla Margarita, Venezuela, Sep. 1999.
1807
Jorge Luis Agüero (SM’01) was born in Mar del
Plata, Argentina, on January 31, 1953. He received
the Engineer degree from La Plata National Univer-
sity, Buenos Aires, Argentina, in 1976.
Since graduation. he has worked in the IITREE-
LAT, a Research and Development University
Institute. He has been Vice-Director of IITREE-LAT
since 2000. He has been a Professor with the
Electrical and Electronic Engineering Department,
Universidad Nacional de La Plata (UNLP), La Plata,
Argentina, since 1983. He was elected as Vice-Dean
of the Engineering Faculty for 1997 to 1998 and re-elected for 1998 to 2001. His
first research dealt with electronic equipment development for nonconventional
electrical measurements. Currently, his research interests include power system
operation and control as well as transient and dynamic behavior of electric
power systems, particularly in the modeling and system tests development.
Mr. Agüero was the Argentina Power Engineering Society Chapter Vice-
Chairman in 1998 and the Chairman in 1999 and 2000.
Patricia Liliana Arnera (SM’00) was born in
Buenos Aires, Argentina, on April 27, 1958. She
received the Electrical Engineering degree from the
Universidad Nacional de La Plata (UNLP), La Plata,
Argentina, in 1981.
She is a Professor of power systems with the
Electrical Engineering Department, School of En-
gineering, UNLP. She has been IITREE director
since 1998. She works for the IITREE-UNLP
studying transient conditions of electrical systems
and working in electromagnetic fields and health.
As a researcher for the IITREE, she has made technical works for public and
private companies of electrical service and industry in Argentine. Her special
field of interest includes electrical power systems.
Ms. Arnera was the Argentina Power Engineering Society (PES) Chapter
Chairman in 2001 and 2002. The Argentine Chapter won “Outstanding Large
PES Chapter of the World” by the developed activities in 2001. She has
been with the Representative Chapter of R9 South West (Argentina, Bolivia,
Colombia, Chile, Ecuador, Perü, and Venezuela) since 2004.
Raúl E. Bianchi Lastra (SM’02) was born in La
Plata, Argentina, on October 12, 1955. He received
the Electrical Engineer degree from Engineering
School, La Plata National University, Buenos Aires,
Argentina, in 1980.
Since graduation and until 1993, he worked in
the Energy Organism of Buenos Aires State (DEBA,
later named ESEBA). Also, he has worked in the
IITREE-LAT, a Research and Development Univer-
sity Institute, since 1986. He first began researching
in the area of electromagnetic transients in power
systems and later in power systems static and dynamic analyses. Currently, his
research interests include power systems operation, dynamics, and transients.
Mario César Beroqui was born in La Plata, Ar-
gentina, on April 10, 1952. He received the Engineer
degree from Engineering School, La Plata National
University, Buenos Aires, Argentina, in 1976.
Since graduation, he has worked in the En-
gineering Faculty, La Plata National University.
He has worked in the IITREE-LAT since 1986, a
Research and Development University Institute.
He first began researching in the control process
area. Currently, his research interests include power
systems operation, dynamics, and control, especially
frequency control.