Supertex inc.

TD9944

Dual N-Channel Enhancement-Mode

Vertical DMOS FET
Features General Description
► Dual N-channel devices This low threshold, enhancement-mode (normally-off)
► Low threshold – 2.0V max. transistor utilizes a vertical DMOS structure and Supertex’s
► High input impedance well-proven, silicon-gate manufacturing process. This
► Low input capacitance – 125pF max. combination produces a device with the power handling
► Fast switching speeds capabilities of bipolar transistors and the high input
impedance and positive temperature coeficient inherent
► Low on-resistance
in MOS devices. Characteristic of all MOS structures, this
► Free from secondary breakdown
device is free from thermal runaway and thermally-induced
► Low input and output leakage
secondary breakdown.

Applications Supertex’s vertical DMOS FETs are ideally suited to a

► Logic level interfaces – ideal for TTL and CMOS wide range of switching and amplifying applications where
► Solid state relays very low threshold voltage, high breakdown voltage, high
► Battery operated systems input impedance, low input capacitance, and fast switching
► Photo voltaic drives speeds are desired.
► Analog switches
► General purpose line drivers
► Telecom switches

Ordering Information Product Summary

Part Number Package Option Packing RDS(ON) ID(ON) VGS(th)
BVDSS/BVDGS
(max) (min) (max)
TD9944TG-G 8-Lead SOIC 2000/Reel
-G denotes a lead (Pb)-free / RoHS compliant package. 240V 6.0Ω 1.0A 2.0V

Absolute Maximum Ratings Pin Coniguration

Parameter Value D2
D2
Drain-to-source voltage BVDSS D1
D1
Drain-to-gate voltage BVDGS
G2
Gate-to-source voltage ±20V S2
G1
Operating and storage temperature -55OC to +150OC S1
Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these conditions is not implied. Continuous operation 8-Lead SOIC
of the device at the absolute rating level may affect device reliability. All voltages are
referenced to device ground.
Product Marking
Typical Thermal Resistance
TD99 YY = Year Sealed
Package θja 44TG WW = Week Sealed
TO-243AA (SOT-89) 133OC/W YYWW = “Green” Packaging
Note:
Mounted on FR5 Board, 25mm x 25mm x 1.57mm Package may or may not include the following marks: Si or
8-Lead SOIC

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 TD9944
Electrical Characteristics (T A
= 25OC unless otherwise speciied)

Sym Parameter Min Typ Max Units Conditions

BVDSS Drain-to-source breakdown voltage 240 - - V VGS = 0V, ID = 2.0mA
VGS(th) Gate threshold voltage 0.6 - 2.0 V VGS = VDS, ID= 1.0mA
ΔVGS(th) Change in VGS(th) with temperature - - -5.0 mV/OC VGS = VDS, ID= 1.0mA
IGSS Gate body leakage - - 100 nA VGS = ± 20V, VDS = 0V
- - 10 µA VGS = 0V, VDS = Max Rating
IDSS Zero gate voltage drain current VDS = 0.8Max Rating,
- - 1.0 mA
VGS = 0V, TA = 125°C
0.5 1.9 - VGS = 4.5V, VDS = 25V
ID(ON) ON-state drain current A
1.0 2.8 - VGS = 10V, VDS = 25V
- 4.0 6.0 VGS = 4.5V, ID = 250mA
RDS(ON) Static drain-to-source on-state resistance Ω
- 4.0 6.0 VGS = 10V, ID = 0.5A
ΔRDS(ON) Change in RDS(ON) with temperature - - 1.4 %/OC VGS = 10V, ID = 0.5A
GFS Forward transductance 300 600 - mmho VDS = 20V, ID = 0.5A
CISS Input capacitance - 65 125
VGS = 0V,
COSS Common source output capacitance - 35 70 pF VDS = 25V,
f = 1.0MHz
CRSS Reverse transfer capacitance - 10 25
td(ON) Turn-on delay time - - 10
VDD = 25V,
tr Rise time - - 10
ns ID = 1.0A,
td(OFF) Turn-off delay time - - 20 RGEN = 25Ω
tf Fall time - - 20
VSD Diode forward voltage drop - - 1.8 V VGS = 0V, ISD = 1.0A
trr Reverse recovery time - 300 - ns VGS = 0V, ISD = 1.0A
Notes:
1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

10V 90% VDD
INPUT Pulse RL
10% Generator
0V OUTPUT
t(ON) t(OFF)
RGEN
td(ON) tr td(OFF) tf

VDD INPUT D.U.T.

10% 10%
OUTPUT
0V 90% 90%

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 TD9944
Typical Performance Curves
4.0
Output Characteristics Saturation Characteristics
2.5

VGS =10V
3.2 2.0
8V
VGS =10V 6V

8V

ID (amperes)
ID (amperes)

2.4 1.5
6V 4V

1.6 1.0
4V
3V
0.8 0.5
3V

2V 2V
0 0
0 10 20 30 40 50 0 2 4 6 8 10
VDS (volts) VDS (volts)

BVDSS Variation with Temperature On-Resistance vs. Drain Current

10

1.1

8 VGS =4.5V
BVDSS (normalized)

VGS =10V
RDS(ON) (ohms)
6

1.0

0.9

0
-50 0 50 100 150 0 1 2 3 4 5
Tj (°C) ID (amperes)

Transfer Characteristics V(th) and RDS Variation with Temperature

3.0 2.4

25°C 1.4
VDS =25V
2.5
RDS(ON) @ 10V, 0.5A 2.0
TA =-55°C 150°C
1.2
RDS(ON) (normalized)
VGS(th) (normalized)

2.0 V(th) @ 1.0mA

ID (amperes)

1.6

1.5 1.0

1.2
1.0
0.8

0.8
0.5
0.6

0 0.4
0 2.0 4.0 6.0 8.0 10 -50 0 50 100 150
VGS (volts) Tj (°C)

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 TD9944
Typical Performance Curves (cont.)

Capacitance vs. Drain-to-Source Voltage Gate Drive Dynamic Characteristics

200 10
f = 1MHz

VDS = 10V
8
150
C (picofarads)

VGS (volts)
6

100 VDS = 40V

4 150 pF
CISS
50
COSS 2

CRSS 63pF
0 0
0 10 20 30 40 0 0.4 0.8 1.2 1.6 2.0
VDS (volts) QG (nanocoulombs)

Transconductance vs. Drain Current

1.0
VDS = 25V
TA = -55°C
0.8

TA = 25°C
GFS (siemens)

0.6

0.4 TA = 150°C

0.2

0
0 0.8 1.6 2.4 3.2 4.0
ID (amperes)

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 TD9944
8-Lead SOIC (Narrow Body) Package Outline (TG)
4.90x3.90mm body, 1.75mm height (max), 1.27mm pitch
D θ1

Note 1
(Index Area
D/2 x E1/2)
E1 E Gauge
L2
Plane

L Seating
1 θ Plane
L1

Top View View B View B

Note 1
A h
h
A A2
Seating
Plane
A1 e b

Side View A
View A-A

Note:
1. This chamfer feature is optional. A Pin 1 identiier must be located in the index area indicated. The Pin 1 identiier can be: a molded mark/identiier;
an embedded metal marker; or a printed indicator.

Symbol A A1 A2 b D E E1 e h L L1 L2 θ θ1
O
MIN 1.35* 0.10 1.25 0.31 4.80* 5.80* 3.80* 0.25 0.40 0 5O
Dimension 1.27 1.04 0.25
NOM - - - - 4.90 6.00 3.90 - - - -
(mm) BSC REF BSC
O
MAX 1.75 0.25 1.65* 0.51 5.00* 6.20* 4.00* 0.50 1.27 8 15O
JEDEC Registration MS-012, Variation AA, Issue E, Sept. 2005.
* This dimension is not speciied in the JEDEC drawing.
Drawings are not to scale.
Supertex Doc. #: DSPD-8SOLGTG, Version I041309.

(The package drawing(s) in this data sheet may not relect the most current speciications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)

©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited.
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
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