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Sumador Completo Bloque VHDL
Sumador Completo Bloque VHDL
Sumador:
Restador :
SUMADOR_COMPLETO :
entity Sumador4Bits is
end Sumador4Bits ;
component Sumador1Bit
port (
C_i : in std_logic ;
end component;
begin
Sumador1Bit_1 : Sumador1Bit
port map (
end structural ;