EE141

EECS141
EE141 Lecture #19 17

  Energy consumed in N cycles, EN:

EN = CL • VDD2 • n0→1

n0→1 – number of 0→1 transitions in N cycles

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Example: Static 2-input NOR Gate

Assume signal probabilities

A B Out pA=1 = 1/2
0 0 1 pB=1 = 1/2
0 1 0
Then transition probability
1 0 0 p0→1 = pOut=0 x pOut=1
1 1 0
= 3/4 x 1/4 = 3/16
If inputs switch every cycle
α0→1 = 3/16

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Example: Static 2-input NAND Gate

Assume signal probabilities

A B Out pA=1 = 1/2
0 0 1 pB=1 = 1/2
0 1 1
Then transition probability
1 0 1 p0→1 = pOut=0 x pOut=1
1 1 0
= 3/4 x 1/4 = 3/16
If inputs switch every cycle
α0→1 = 3/16

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Example: Static 2-input XOR Gate

Assume signal probabilities
A B Out pA=1 = 1/2
0 0 0 pB=1 = 1/2
0 1 1
Then transition probability
1 0 1 p0→1 = pOut=0 x pOut=1
1 1 0
=
If inputs switch in every cycle
α0→1 =

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CLK Mp
Out
In1 CL
In2 PDN
In3

CLK Me

Power only dissipated when previous Out = 0

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Dynamic 2-input NOR Gate

Assume signal probabilities

A B Out PA=1 = 1/2
0 0 1 PB=1 = 1/2
0 1 0
Then transition probability
1 0 0 P0→1 = Pout=0 x Pout=1
1 1 0
= 3/4 x 1 = 3/4
Switching activity always higher in dynamic gates!
P0→1 = Pout=0

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  Always switches
  Often consumes 25-50% of total power
  Clock gating commonly employed

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P(Z = 1) = P(B = 1) . P(X = 1 | B=1)

Becomes complex and intractable fast

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Logic without Logic with

reconvergent fanout reconvergent fanout

p0→1 = (1 – pApB) pApB P(Z = 1) = p(C=1 | B=1) p(B=1)

p0→1 = 0
  Need to use conditional probabilities to model
inter-signal correlations
  CAD tools best for performing such analysis

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ABC 101 000

Z
Also known as
Gate Delay dynamic hazards

The result is correct,

but there is extra power dissipated

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  Mostimportant idea: reduce waste

  Examples:
  Don’t switch capacitors you don’t need to
–  Clock gating, glitch elimination, logic re-structuring
  Don’t run circuits faster than needed
–  Power α VDD2 – can save a lot by reducing supply for
circuits that don’t need to be as fast
–  Parallelism falls into this category
  Let’s say we do a good job of that – then
what?

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Energy/op
Performance
  Plot all possible designs on a 2-D plane
  No matter what you do, can never get below/to the
right of the solid line
  This line is called “Pareto Optimal Curve”
  Usually (always) follows law of diminishing returns

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Energy/op

Performance
  Instead of metrics like EDP, this curve often
provides information more directly
  Ex1: What is minimum energy for XX performance?
  Ex2: Over what range of performance is a new
technique (dotted line) actually beneficial?

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