D A NAVANEETH REDDY

Mobile: +91- 9110304920 Email: navaneeth434.d@gmail.com

PROFESSIONAL SUMMARY

Dedicated, professional seeks VLSI design engineer position to work for an

organization which pro- vides me the opportunity to improve my skills and
knowledge growing along with the organization’s objective.

ACADEMICS

 Bachelor Degree in Electronics & Communication – 2018, Santhiram Engineering

College, JNTUA with 7.1CGPA.
 Sree Chaitanya Junior College, Board - Intermediate with 86.7 % / 12th – 2014.
 Indus Enghlish Medium School, Board - SSC with 90 % / 10th -2012.

TECHNICAL SKILLS

Hardware Description language Verilog

Programming Language C, H-SPICE

EDA Tool Synopsys IC Compiler(28nm), Prime Time,
StarRC, Custom designer(28nm)

Other Tools Modelsim,Tanneer.

Scripting Language TCL(basic)

Operating System Windows, Linux

INTERNSHIPS/TRAININGS

Physical Design Training from VLSI guru training Institute Bangalore, Using
Synopsys IC Compiler from Aug 2018 to Feb 2018.

COURSE OUTLINE

 Fundamentals of Digital electronics, CMOS Design, SRAM, Floor planning,

Placement, Clock Tree Synthesis, Routing, Timing Closure, Physical
Veriftcation(DRC, LVS, ANT), ECO flow .
PROJECTS

 Physical Design Implementation (RTL netlist to GDS II) of SoC sub- system
Physical Design Training

Type of service : Physical Design

Technology/Layer : 8nm/9 metal layer
Number of Macros : 40
Complexicity : 52K Standard cells
No. of Clock : 8
Frequency : 416 MHz
Tool Used : Synopsys IC-Compiler, STAR RC, Prime Time
Role Setting initial Floorplan, setting Powerplan to
meet the power budget (IR drop analysis),
Physical synthesis with timing and congestion
driven placement, CTS to optimize clock skew
and minimize clock latency and Routing. Also,
it includes physical verification steps like
DRC,LVS,ERC Also, analyzing timing re- port
and fixing timing violations in Pre and Post-
layout STA.

ACADEMIC PROJECT:(B.Tech)

Title: Low power BCD Adder by using majority gate.

 Majority gate cmos technology has become one of the most attractive approaches for the
development of the next generation ultra- dense low-power digital circuits.
 Total power dissipated in a cmos circuit is sum total of dynamic power, short circuit
power and static or leakage power.design for low-power.
 The ability to reduce all the components of power consumption in cmos circuits during
the development of a low power electronic product.
Tools used: Tanner Tools.

STRENGTH

 Active learning
 Positive Atitude, Hardworking

DECLARATION

I declare that all the information furnished above is factually correct and true to the best of my
knowledge and belief.

Place:Bangalore. D.A.NavaneethReddy.