Table of Content

1-Pipelining Hazards and Solutions ........................................................................1

1-1: What is Pipelining in Computer Architecture?................................................2
1-2: Performance Equation of Pipelining ...............................................................2
1-2.1: Advantages of Pipelining .....................................................................2
1-2.2: Disadvantages of Pipelining ................................................................2
1-3: What are the Pipelining Hazards? ................................................................ 2
1-3:Data Hazards ...........................................................................................2
1-3: Control Hazards .....................................................................................2
1-3: Structure Hazards ...................................................................................2
1.3.1 Data Hazard ...................................................................................................3
1-3.1.1: Example of Data Hazard and explanation ..........................................3
1-3.1.2: Solution of Data Hazard ...................................................................4
1-3.1.3: Classification of Data Hazard ......................................................... 4-5
1.3.2 Control Hazard ..............................................................................................5
1-3.2.1: What happens in Control Hazard (with/without pipelining)? ........ 5-6
1-3.2.2: Solution of Control Hazard ..............................................................6
1.3.3 Structural Hazard ..........................................................................................6
1-3.3.1: Example of Structural Hazard and explanation .................................7
1-3.3.2: Solution of Structural Hazard ..........................................................7
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1- Pipelining Hazards and Solutions

1-1: What is Pipelining in Computer Architecture?

Pipelining is a process of Simultaneous execution of more than one instruction
which takes place in a pipelined processor. Pipeline is divided into stages and
these stages are connected with one another to form a pipe like structure.
Instructions enter from one end and exit from another end. An instruction
pipeline reads instruction from the memory while previous instructions are being
executed in other segments of the pipeline. Thus we can execute multiple
instructions simultaneously. The pipeline will be more efficient if the instruction
cycle is divided into segments of equal duration. This is the example of ILP
(instructional level parallelism). It has following stages:
Stage 1 (Instruction Fetch)
In this stage the CPU reads instructions from the address in the memory
Stage 2 (Instruction Decode)
In this stage, instruction is decoded and the register file is accessed to get the
values from the registers used in the instruction.
Stage 3 (Instruction Execute)
In this stage, ALU operations are performed.
Stage 4 (Memory Access)
In this stage, memory operands are read and written from/to the memory that is
present in the instruction.
Stage 5 (Write Back)
In this stage, computed/fetched value is written back to the register present in
the instructions.
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1-2: Performance Equation of Pipelining:

k = no of stages/stages
n= tasks to be completed in the pipelined processor.
tp = clock cycle time taken by process
Now, the first instruction is going to take k those many clock pulses as is number
of segments, but the other n – 1 instruction will take only 1 clock cycle each after
the completion of first instruction
Pipeline= (k+ n - 1) tp
1-2.1: Advantages of Pipelining
The cycle time of the processor is reduced.
It increases the throughput of the system
It makes the system reliable.
1-2.2: Disadvantages of Pipelining
The design of pipelined processor is complex and costly to manufacture.
The instruction latency is more.

1-3: What are the Pipelining Hazards?

There are situations, called hazards that prevent the next instruction in the
instruction stream from being executing during its designated clock cycle. Hazards
reduce the performance from the ideal speedup gained by pipelining and produce
incorrect result.
There are 3 Classes for hazards:
1- Data Hazard
2- Control Hazard
3- Structural Hazard
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1-3.1: Data Hazard:

Occur when given instruction depends on data from an instruction ahead of it in
pipeline. It will going to affect your performance overall
By explain following example it will be clearer

1-3.1.1: Example of Data Hazard:

Consider following instructions
ADD R1, R2, R3
SUB R4, R5, R1

Explanation:
In this instruction we have to add the content of R2 and R3 and save the result in
R1 address same goes with 2nd instruction. We have to read the content of R2 and
R3
In 1st instruction will be in fetch then buffer 1 will have instruction 1. In decode
2nd clock cycle step it will generate the controlling signals based on input and R1
will be read, in buffer 2 content of R2 and R3 , address of R1 will be read. Since we
know that Execution is nothing but ALU so suppose R2=20 and R3=30 their sum
will be in execution buffer which is 50 also along with R1 address. Memory stage
nothing has to do on this stage it will simply forward it to write back that will
simply assign 50 to &R1. The process with ADD R1, R2, and R3 has been
completed.
Now let’s talk about SUB R4,R5,R1 after 2nd clock cycle start process of this
instruction2 will fetch in buffer, after 3rd it will decode and so on then there will
be problem occur after 3rd clock cycle, in 1st instruction R1 has updated after
memory write back but in 3rd clock cycle value of R1 initially upper is 0 so
subtraction will not perform and we have to stop pipelining at that stage if we
start this process after 1st wb the 3 slots will go empty and space and time will
waste here occur Data Hazard. Now how to deal with it?
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1-3.1.2: Solution of Data Hazard:

(i) Stalling: while see if there is dependency between the instructions in
software level so the next fetch will be stopped and design your
hardware in such way that start fetching next instruction after the
instruction1 will be completed

(ii) Forwarding. : The problem with data hazards, introduced by this

sequence of instructions can be solved with a simple hardware
technique called forwarding. As we see the result will surly available
after write back stage in register but throughout this process the 50 is
lying somewhere we connect it via designing hardware in such way
using multiplexer that will tell from where we have to take data from
original location or from buffer of previous instruction then execution
stage will take either data from upper cable or from decode stage, the
data in the execution/memory buffer will be forwarded to
Data/execution buffer.R1 will be bypassed as we use another
connection to get data. Last but not the least backward forwarding is
not possible at all we use stall for it

1-3.1.3: Classification of Data Hazard:

RAW (read after write)
WAW (write after write)
WAR (write after read)
Consider two instructions i and j, with i occurring before j. The possible data
hazards are:
RAW (read after write) - j tries to read a source before i writes it, so j incorrectly
gets the old value.
WAW (write after write) - j tries to write an operand before it is written by i. The
writes end up being performed in the wrong order, leaving the value written by i
rather than the value written by j in the destination.
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WAR (write after read) - j tries to write a destination before it is read by i , so i

incorrectly gets the new value.

1-3.2: Control Hazard (Branch Hazard):

Control Hazard Occur due to the branch instruction .In order to fetch and execute
the next instruction, we must know what that instruction is. If the present
instruction is a branch, and its result will lead us to the next instruction, then the
next instruction may not be known until the current one is processed. The
processor will not know the outcome of the branch when it needs to insert a new
instruction into the pipeline it may or may not change the program counter.
Branching is a basic concept It means an instruction that tells a computer to begin
executing a different part of a program rather than executing statements one-by-
one

1-3.2.1: What generally happens in Control Hazard (with/without

pipelining)?
Without Pipelining:
In general while working with control hazard the execution of statement
L1 BEQ R1, R2, 50
Instruction is fetch which is L1, Then appropriate identifiers will create and it will
go to execute stage where the initial value of program counter is 100, when we
fetch the instruction1 the PC will increment to 104, after R1 and R2 will compare
in execution stage if they both are equal then effective address of memory will
become 104+50 =154, if they both are not equal then PC will not update. PC
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In memory stage nothing will happen. In WB 154 is the effective address with
write back to execution buffer and update PC and next instruction is on EA 154

With Pipelining:
Fetch the instruction 1 the PC is 100 initially on execution stage if R1 and R2 are
not equal to each other then we will follow the regular pipelining process which is
perfectly fine but what if it is false? If R2 and R1 are equal EA=154 then execute
104, 108 is wastage of resources and time. We then identify the branch on
execution stage if it’s unsuccessful its fine but if it’s successful problem will occur

1-3.2.2: Solution of Data Hazard:

(i) Pipeline Flushing: generally on 3rd stage which is execution we realize
that R1 and R2 are equal (Branch success) and all that fetching execution
we do for other instructions are gone waste so we use mechanism called
Flushing pipeline in after realization we generate control signals for
fetch and decode instruction flushing signals which is 0 so that it will not
create problem at all. And our resources will not go waste (dummy
instruction will take place). It will waste 2 stall cycles

(ii) Early Branch Detection: in this method we realize it on 2nd stage which
is decoding stage and optimize the stall to 1 instead of 2 because
sometimes execution is very fast. We use extra circulatory component
to predict the comparison on decode stage instead of execution stage.
You will realized that which instruction to be fetch next

1-3.3: Structural Hazard:

Structural Hazard occurs when two instructions need the resources of
hardware at the same time, it can be same register, memory or ALU in a
same clock cycle that result in conflicts. Even compiler or programmer
can do it.
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1-3.3.1: Example of Structural Hazard:

Consider the Following Example and made instruction table
ADD R1, R2, R3 : ADD R4, R5, R6 : SUB R7, R8, R1
We have to add R2 and R3 and save result in Register1 same case with
instruction2 and 3

One after another we are doing stages with each instruction, fetch decode,
execute and write back result in memory but if we notice on 4th clock cycle is
needed for decoding and fetching the operand this phase is needed for 2 things
R1 is needed for fetching the operand and storing the result in same clock pulse
here inconsistency arises which is structural Hazard. What to do now?

1-3.3.3: Solution of Structural Hazard:

(i) Pipeline Bubbling : since in above example Instruction3 is coming after
Instruction1 so delay the decoding phase of Ins3 till done with Ins1

(ii) Duplicate: Add more hardware to design so that each instruction will
separately access their resources