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Systemc: Aleksandar Milenkovic The University of Alabama in Huntsville Email: Milenka@Ece - Uah.Edu
Systemc: Aleksandar Milenkovic The University of Alabama in Huntsville Email: Milenka@Ece - Uah.Edu
Aleksandar Milenkovic
The University of Alabama in Huntsville
Email: milenka@ece.uah.edu
Outline
n Introduction
n Data Types
n Modeling Combinational Logic
n Modeling Synchronous Logic
n Misc
n What is SystemC?
n Why SystemC?
n Design Methodology
n Capabilities
n SystemC RTL
same specification
Compiler
Linker SystemC
Class Library and
Debugger
Simulation Kernel
Source files in
Make
SystemC
(design + testbenches)
Simulator
executable
Run
Test input files Test, log output files
Chip
Slowest
Synthesize
To implementation
Refine SystemC
Write testbench model to RTL
Reverify
Reuse testbench
Synthesize
To implementation
SC_MODULE(half_adder) { void
sc_in<bool> a, b; half_adder::prc_half_adder() {
sc_out<bool> sum, carry; sum = a ^ b;
carry = a & b;
void prc_half_adder(); }
SC_CTOR(half_adder) {
SC_METHOD(prc_half_adder);
sensitive << a << b;
}
};
}
};
full_adder f1(“FullAdderWithHalfAdders”);
f1 << t_a << t_b << t_cin << t_sum << t_cout;
driver d1(“GenWaveforms”);
d1.d_a(t_a);
d1.d_b(t_b);
d1.d_cin(t_cin);
monitor m1(“MonitorWaveforms”);
m1 << t_a << t_b << t_cin << t_sum << t_cout;
sc_start(100, SC_NS);
return(0);
}