Systemc 1 Tutorial

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½ This tutorial offers

½ A short motivation for C based design flow
½ A brief introduction to the most important SystemC 1.0.x
language elements
½ A very short overview on refinement for synthesis
½ A simple example program
½ This tutorial does not

½ provide a complete treatment of the SystemC language
½ cover system level modeling with SystemC 2.0
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Unit Topic
1 SystemC Introduction
2 Language Elements of SystemC
3 SystemC and Synthesis
4 Simple Example
5 Resources
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C/C++
4. Hand over specification document HDL
1. Conceptualize
2. Simulate in C++ 5. Understand
3. Write specification 6. (Re)Implement in HDL
document 7. (Re)Verify
8. Synthesize from HDL
Problems:Written specifications are incomplete and inconsistent

Translation to HDL is time consuming and error prone
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C/C++
C/C++
C/C++
1. Conceptualize
2. Simulate in C++
3. Write specification
document
4. Hand over
• Executable specification
• Testbench
• Written specification
5. Understand
6. Refine in C++
7. Verify reusing testbenches
8. Synthesize from C++
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½ SystemC supports
½ Hardware style communication
½ Signals, protocols, etc.
½ Notion of time
½ Time sequenced operations.
½ Concurrency
½ Hardware and systems are inherently concurrent, i.e. they operate in
parallel.
½ Reactivity
½ Hardware is inherently reactive, it responds to stimuli and is in
constant interaction with its environment, which requires handling of
exceptions.
½ Hardware data types
½ Bit type, bit-vector type, multi-valued logic type, signed and unsigned
integer types and fixed-point types.
½ Integrated Simulation Kernel
½ All these features are not supported by C++ as is IIS

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Software UTF Hardware
UTF ½ System/ Architectural Level
½not synthesizable
Refine ½event driven
½abstract communication
TF
TF ½abstract data types
Refine
½ Behavioral Level
Partition
½synthesizable
½clocked
Behavioral
Behavioral ½I/O cycle accurate
½algorithmic description
abstract Refine
abstract
RTOS
RTOS RTL
RTL ½ RT Level
Refine ½synthesizable
½clocked
target
target ½FSM
code Netlist
Netlist ½data path
code
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your standard
C/C++ development
environment DSP
header files Interface
compiler
IP-Core
.......
libraries
linker ASIC
class library debugger

and
....
simulation kernel source files for system
and testbenches
make
t able n“
x ecu atio
„e ecific sim.x
sp
executable = simulator
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Channel
Channel (implements
(implements I/F)
I/F) SystemC 2.x
Port
Port (accesses
(accesses aa channel’s
channel’s I/F)
I/F)
o Module
o Port
o Interface
Module o Channel
o Process
Interface
Interface
Algorithm
Process
Process (reads
(reads data
data from
from input
input ports
ports IIS
and writes data to output ports)
and writes data to output ports) Fraunhofer Institut
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Hardware
Hardware signal
signal
Special SystemC 1.0.x
Special ports
ports to
to access
access the
the hardware
hardware signal
signal
o Module
o Special Ports
o Hardware Signal
Module o Process
Algorithm
Process
Process (reads
(reads data
data from
from input
input ports
ports IIS
and writes data to output ports)
and writes data to output ports) Fraunhofer Institut
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main.cpp
in1 in2
a1 in1
Stimulus Response
DUT out re
Generator Monitor
a2 in2
clk
Algorithm
stimgen.cpp
stimgen.cpp algo.cpp
algo.cpp monitor.cpp
monitor.cpp
stimgen.h
stimgen.h algo.h
algo.h monitor.h
monitor.h
DUT
out
main.cpp
main.cpp
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VHDL SystemC
½ Hierarchy entity module
½ Connection port port
½ Communication signal signal
½ Functionality process process
½ Test Bench object orientation
½ System Level channel, interface, event
abstract data types
½ I/O simple file I/O C++ I/O capabilities
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Unit Topic
1 SystemC Introduction
4 Simple Example
5 Resources
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Unit Topic
2.1 Data Types
2.1 Modules, Ports and Signals
2.2 Processes
2.3 Hierarchy
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½ C++ built in data types may be used but are not adequate to
model Hardware.
½ long, int, short, char, unsigned long, unsigned int,
unsigned short, unsigned char, float, double, long double,
and bool.
½ SystemCTM provides other types that are needed for System

modeling.
½ Scalar boolean types: sc_logic, sc_bit
½ Vector boolean types: sc_bv<length>, sc_lv<length>
½ Integer types: sc_int<length>, sc_uint<length>,
sc_bigint<length>, sc_biguint<length>
½ Fixed point types: sc_fixed, sc_ufixed
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To get fast simulations, you have to choose the right data type
½use builtin C/C++ data types as much as possible

Fastest ½use sc_int/sc_uint
½ integer with up to 64 bits
½ model arithmetic and logic operations
½use sc_bit/sc_bv
½ arbitrary length bit vector
Slowest
½ model logic operations on bit vectors
½ two valued logic
½use sc_logic/sc_lv
½ 4 valued logic vectors
½ model tri-state behavior
Hint: You may use a profiling tool, which tells you, how much
time you spent in which function call, to control simulation
speed.
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To get fast simulations, you have to choose the right data type
Fastest ½use sc_bigint/sc_biguint

½ integer with arbitrary length
½ use to model arithmetic operations on large bit vectors
½ ineffective for logic operations
½use sc_fixed/sc_ufixed
Slowest
½ arbitrary precision fixed point
½ use to model fixed point artihmetic
½ ineffective for logic operations
Hint: You may use a profiling tool, which tells you, how much
time you spent in which function call, to control simulation
speed.
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Syntax:
Syntax:
sc_int<length>
sc_int<length> variable_name
variable_name;;
sc_uint<length>
sc_uint<length> variable_name
variable_name;;
sc_bigint<length>
sc_bigint<length> variable_name
variable_name;;
sc_biguint<length>
sc_biguint<length> variable_name
variable_name;;
length:
length:
½½ Specifies
Specifiesthe
thenumber
numberof ofelements
elementsininthe
thearray
array
½½ Must
Mustbebegreater
greaterthan
than00
½½ Must
Mustbebecompile
compiletime
timeconstant
constant
½½ Use
Use [] to bit select and range()to
[] to bit select and range() topart
partselect.
select.
½½ Rightmost
Rightmostis isLSB(0),
LSB(0),Leftmost
Leftmostis isMSB
MSB(n-1)
(n-1)
sc_int<5>
sc_int<5> a;a; //
// aa is
is aa 5-bit
5-bit signed
signed integer
integer
sc_uint<44>
sc_uint<44> b; b; //
// bb is
is aa 44-bit
44-bit unsigned
unsigned integer
integer
sc_bigint<5>
sc_bigint<5> c; c;
cc == 13;
13; // c gets 01101,
// c gets 01101, c[4]
c[4] == 0,
0, c[3]
c[3] == 1,
1, …,
…, a[0]
a[0] == 11
bool
bool d;
d;
dd == c[4];
c[4]; //
// dd gets
gets 00
dd == c[3];
c[3]; //
// dd gets
gets 11
sc_bigint<3>
sc_bigint<3> e; e;
ee == c.range(3,
c.range(3, 1);
1); //
// ee gets
gets 110
110 -- interpreted
interpreted asas -2
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Unit Topic
2.1 Data Types
2.2 Processes
2.3 Hierarchy
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½ A module is a container. It is the
basic building block of SystemC main.cpp
½ Similar to VHDL “entity” a1 in1
Stimulus Response
DUT out re
Generator Monitor
½ Module interface in the header file a2 in2
(ending .h) clk
½ Module functionality in the

implementation file (ending .cpp)
½ Module contains: stimgen.cpp algo.cpp monitor.cpp

stimgen.cpp algo.cpp monitor.cpp
½ Ports
stimgen.h
stimgen.h algo.h
algo.h monitor.h
monitor.h
½ Internal signal variables
½ Internal data variables
½ Processes of different types
main.cpp
½ Other methods main.cpp
½ Instances of other modules

½ Constructor IIS
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SC_MODULE
Syntax:
Syntax: {
o Ports
SC_MODULE(module_name){
SC_MODULE(module_name){ o Signals
o Variables
//
// body
body of
of module
module o Constructor
o Processes
};
}; o Modules
};
EXAMPLE: Code
Codeininheader
headerfile:
file:
EXAMPLE: my_module.h
my_module.h
SC_MODULE(my_module)
SC_MODULE(my_module){{
////body
bodyofofmodule
module
};};
Note
Notethe
thesemicolon
semicolonat
atthe
the
end
endofofthe
themodule
moduledefinition
definition
Note: SC_MODULE is a macro for

struct module_name : sc_module
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Signal Ports
Ports bound
bound directly
directly to
to SC_MODULE
Signal connecting
connecting modules
modules (declared
(declared in
in
module) each
each other
other (no
(no signal)
signal) {
module)
o Ports
o Signals
o Variables
Ports
Ports o Constructor
Module Module o Processes
Module Module o Modules
};
Instance
Instance Instance
Instance
MODULE
Other
Other
Method
Method
Process
Process
Other
Other methods
methods cancan
read/write
read/write ports
ports and
and signals
signals
Process
Process can
can read/write
read/write
ports
ports and
and signals
signals IIS
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½ Ports are the external interface of a module SC_MODULE
{
½ Pass information to and from a module ã Ports
o Signals
½ There are three different kinds of ports o Variables
o Constructor
½ input o Processes
o Modules
½ output };
½ inout
½ Ports are always bound to signals
½ exception: port-to-port binding (explained later)
½ Ports are members of the module
½ Each port has a data type
½ passed as template parameter
main.cpp
a1 in1
Stimulus Response
DUT out re
Generator Monitor
a2 in2
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SC_MODULE
{
½ Ports have to be declared inside a module ã Ports
o Signals
½ The direction of the port is specified by the port type o Variables
o Constructor
½ input: sc_in<> o Processes
o Modules
½ output: sc_out<> };
½ inout: sc_inout<>
½ The data type is passed as template parameter
Declaration
Declarationas
asdata
datamembers
membersof
ofthe
themodule:
module:
SC_MODULE(my_mod)
SC_MODULE(my_mod) { {
sc_in<t_data>
sc_in<t_data> port_name;
port_name;
sc_out<t_data>
sc_out<t_data> port_name;
port_name;
sc_inout<t_data>
sc_inout<t_data> port_name;
port_name;
};
};
t_data:
t_data:
½½ data
datatype
typeof
ofthe
theport
port
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½ Signals are used for communication SC_MODULE
{
½ Exchange of data in a concurrent execution semantics o Ports
ã Signals
½ between modules o Variables
o Constructor
½ between processes o Processes
o Modules
½ There is only one kind of signal };
½ Signals always carry a value

½ Signals need not necessarily be bound to ports
½ may also be used for communication between processes
½ Signals may be
½ members of a module (used for internal communication)
½ used at top-level to connect the modules
½ Each signal has a data type main.cpp
½ passed as template parameter a1 in1
Stimulus Response
DUT out re
Generator Monitor
a2 in2
clk
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SC_MODULE
½ Signals are declared inside a module or at top level {
o Ports
½ There is only one type of signal ã Signals
o Variables
½ sc_signal<> o Constructor
o Processes
½ The data type is passed as template parameter o Modules
};
Declaration
Declarationas
asdata
datamembers
membersof
ofthe
themodule:
module:
SC_MODULE(my_mod)
SC_MODULE(my_mod) { {
sc_signal<t_data>
sc_signal<t_data> signal_name;
signal_name;
};
};
t_data:
t_data:
½½ data
datatype
typeof
ofthe
thesignal
signal
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SC_MODULE
½ Declaring ports and signals within a module {
ã Ports
½ ports and signals are data members of the module ã Signals
o Variables
½ good style to declare o Constructor
o Processes
½ ports at the beginning of the module o Modules
};
½ signals after port declaration
SC_MODULE(module_name)
SC_MODULE(module_name) {{
//
// ports
ports
sc_in<int>
sc_in<int> a; Note:
a; Note:aaspace
spaceisis
sc_out<bool>
sc_out<bool> b; required
b; requiredby
bythe
theC++
C++
sc_inout<sc_bit>
sc_inout<sc_bit> c;
c; compiler
compiler
//
// signals
signals
sc_signal<int>
sc_signal<int> d;
d;
sc_signal<char>
sc_signal<char> e;
e;
sc_signal<sc_int<10>
sc_signal<sc_int<10> >> f;
f;
//
// rest
rest
}; IIS
}; Fraunhofer Institut
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½ To read a value from a port or signal SC_MODULE
{
½ use assignment ã Ports
½ use the .read() method (recommended) ã Signals
o Variables
o Constructor
o Processes
½ To write a value to a port or signal o Modules
};
½ use assignment
½ use the .write() method (recommended)
½ The usage of .read() and .write() avoids implicit type conversion,

which is a source of many compile time errors
recommended
recommended
sc_signal<int>
sc_signal<int> sig; sc_signal<int>
sig; sc_signal<int> sig;
sig;
int
int a; int
a; int a;
a;
...
... ...
...
aa == sig;
sig; aa == sig.read();
sig.read();
sig
sig == 10;
10; sig.write(10);
sig.write(10);
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SC_MODULE
½ Data variables are member variables of a module {
o Ports
½ any legal C/C++ and SystemC/user defined data type o Signals
ã Variables
½ internal to the module o Constructor
o Processes
½ should not be used outside of the module o Modules
};
½ useful to store the internal state of a module
½ e.g. usage as memory
Example:
Example:
SC_MODULE(count)
SC_MODULE(count) {{
//
// ports
ports && signals
signals not
not shown
shown
int
int count_val;
count_val; //// internal
internal data
data stroage
stroage
sc_int<8>
sc_int<8> mem[512]
mem[512] //
// array
array of
of sc_int
sc_int
//
// Body
Body of
of module
module not
not shown
shown
};
};
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SC_MODULE
{
o Ports
½ Each module has a constructor o Signals
o Variables
½ Called at the instantiation of the module ã Constructor
o Processes
½ initialize internal data structure (e.g. check port-signal o Modules
binding) };
½ initialize all data members of the module to a known state

½ Instance name passed as argument
½ useful for debugging/error reporting
½ Processes are registered inside the constructor (more
later)
½ Sub-modules are instanciated inside the constructor
(more later)
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Code
Codein
inheader
headerfile:
file: SC_MODULE
Example:
Example: {
module_name.h
module_name.h o Ports
o Signals
SC_MODULE
SC_MODULE (my_module)
(my_module) {{ o Variables
//
// Ports,
Ports, internal
internal signals,
signals, processes,
processes, other
other methods
methods ã Constructor
//
// Constructor
Constructor o Processes
o Modules
SC_CTOR(my_module)
SC_CTOR(my_module) {{ };
//
// process
process registration
registration && declarations
declarations ofof sensitivity
sensitivity lists
lists
//
// module
module instantiations
instantiations && port
port connection
connection declarations
declarations
}}
};
};
Note: SC_CTOR is a macro for

typedef name SC_CURRENT_USER_MODULE; \
name(sc_module_name)
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Unit Topic
2.1 Data Types
2.2 Processes
2.3 Hierarchy
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SC_MODULE
{
o Ports
½ Functionality of a SystemC model is described in processes. o Signals
o Variables
o Constructor
½ Processes are member functions of a module. They are registered ã Processes
o Modules
to the SystemC simulation kernel. };
½ Processes are called by the simulation kernel, whenever a signal in
their sensitivity list is changing.
½ Some processes execute when called and return control to the calling
function (behave like a function).
½ Some processes are called once, and then can suspend themselves
and resume execution later (behave like threads).
½ Processes are not hierarchical

½ Cannot have a process inside another process (use module for
hierarchical design)
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SC_MODULE
{
o Ports
o Signals
½ Processes use signals to communicate with each other. o Variables
½ Don’t use global variables - may cause order dependencies in o Constructor
ã Processes
code (very bad). o Modules
};
½ Processes use timing control statements to implement

synchronization and writing of signals in processes (explained
later).
½ Process and signal updates follow the evaluate-update

semantics of SystemC.
½ Processes are registered to the simulation kernel within the

module’s constructor.
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SC_MODULE
½ SC_METHOD (sc_async_fprocess) {
o Ports
½ process executes everything and wakes up at next event o Signals
o Variables
½ good for modeling combinational logic o Constructor
ã Processes
½ synchronous logic is sensitive to clock edge o Modules
};
½ SC_THREAD (sc_async_tprocess)
½ execution is suspended on wait() until next event
½ SC_CTHREAD (sc_sync_tprocess)
½ execution is suspended on wait() until next active clock edge
½ within one process can be only registers sensitive to one clock
edge
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Processes
ã SC_METHOD
½ Asynchronous Function Process SC_METHOD: o SC_THREAD
o SC_CTHREAD
½ Is sensitive to a set of signals
½ This set is called sensitivity list
½ May be sensitive to any change on a signal
½ May be sensitive to the positive or negative edge of a boolean
signal
½ Is invoked whenever any of the inputs it is sensitive to changes.

½ Once an asynchronous function process is invoked:
½ Entire body of the block is executed.
½ Instructions are executed infinitely fast (in terms of internal simulation
time).
½ Instructions are executed in order.
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Processes
ã SC_METHOD
o SC_THREAD
½ Asynchronous Function Process SC_METHOD: o SC_CTHREAD
½ Model combinational logic
½ multiplexing, bit extraction, bit manipulation, arith. operations...
½ Model sequential logic

½ use a SC_METHOD process sensitive to only on clock edge to update the
registers
½ use another SC_METHOD process sensitive to all values to be read within
this process to calculate new values
½ Monitor signals as part of a testbench
½ Use for RT level modeling
½ Model event driven systems (architectural level)
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Processes
½ To define the sensitivity list for any process type use ã SC_METHOD
ã SC_THREAD
½ sensitive with the () operator o SC_CTHREAD
½ takes a single port or signal as an argument
½ e.g. sensitive(sig1); sensitive(sig2); sensitive(sig3);
½ sensitive with stream notation (operator <<)

½ takes an arbitrary number of arguments
½ e.g. sensitive << sig1 << sig2 << sig3;
½ sensitive_pos with either () or << operator

½ defines sensitivity to positive edge of boolean signal or clock
½ e.g. sensitive_pos << clk;
½ sensitive_neg with either () or << operator

½ defines sensitivity to negative edge of boolean signal or clock
½ e.g. sensitive_neg << clk;
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Processes
SC_MODULE( my_module ) { ã SC_METHOD
sc_in_clk clk; o SC_THREAD
sc_in<bool> reset_n; o SC_CTHREAD
sc_in<int> in1;
sc_in<int> in2; void my_module::proc1()
{
sc_out<int> out1; int inc = 5;
sc_out<int> out2; inc++;
sc_signal<int> sig1; sig2 = in1.read() + sig1 + inc;
sc_signal<int> sig2; }
int _internal;
void proc1();
SC_CTOR( my_module ) { State

Stateof
ofinternal
internalvariables
variablesnot
notpreserved
preserved
SC_METHOD( proc1 ); =>
sensitive << in1 << sig1; =>expression
expressionevaluates
evaluatestoto
}
sig2
sig2 == in1+sig1+6
in1+sig1+6
}; each
eachtime
timethe
theprocess
processisisexecuted.
executed.
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Processes
o SC_METHOD
½ Asynchronous Thread Process SC_THREAD: ã SC_THREAD
o SC_CTHREAD
½ Is sensitive to a set of signals
½ This set is called sensitivity list
½ May be sensitive to any change on a signal
½ May be sensitive to the positive or negative edge of a boolean signal
½ Is reactivated whenever any of the inputs it is sensitive to changes.

½ Once an asynchronous thread process is reactivated:
½ Instructions are executed infinitely fast (in terms of internal simulation
time) until the next occurrence of a wait() statement.
½ Instructions are executed in order.
½ The next time the process is reactivated execution will continue after the
wait() statement.
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Processes
o SC_METHOD
ã SC_THREAD
o SC_CTHREAD
½ Asynchronous Thread Process SC_THREAD:

½ May be used to model synchronous AND asynchronous behavior
(even in the same process).
½ Most useful at higher levels of abstraction (esp. with SystemC 2.0)
½ Has to be replaced by asynchronous function or synchronous thread

process during refinement.
½ May be used in test benches.
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Processes
½ Implement synchronization and writing of signals in processes. o SC_METHOD

½ wait() suspends execution of the process until the process is ã SC_THREAD
ã SC_CTHREAD
invoked again.
½ If no timing control statement used:

½ Process executes in zero time.
½ Outputs are never visible.
½ To write to an output signal, a process needs to invoke a timing

control statement.
½ Multiple interacting synchronous processes must have at least

one timing control statement in every path.
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Processes
½ wait() may be used in both SC_THREAD and SC_CTHREAD processes
but NOT in an SC_METHOD process (block). o SC_METHOD
ã SC_THREAD
ã SC_CTHREAD
½ wait() suspends execution of the process until the process is
invoked again.
½ wait(<pos_int>) may be used to wait for a certain number of

cycles (SC_CTHREAD only).
½ In Synchronous process (SC_CTHREAD)

½ Statements before the wait() are executed in one cycle.
½ Statements after the wait() are executed the next cycle.
½ In Asynchronous process (SC_THREAD)

½ Statements before the wait() are executed in last event.
½ Statements after the wait() are executed the next event.
Examples:
Examples:
wait()
wait() ;; //
// waits
waits 11 cycle
cycle in
in synchronous
synchronous process
process
wait(4);
wait(4); //// waits
waits 44 cycles
cycles in
in synchronous
synchronous process
process IIS
wait(4) ; //ERROR!! in Asynchronous process Fraunhofer Institut
wait(4) ; //ERROR!! in Asynchronous process
6&B7+5($'
Processes
SC_MODULE( my_module ) { void my_module::proc2() o SC_METHOD
sc_in_clk clk; { ã SC_THREAD
sc_in<bool> reset_n; // start-up functionality goes here o SC_CTHREAD
int inc = 1;
sc_in<int> in1;
sc_in<int> in2; while(1) {
out1.write(in2.read() + sig2 + inc);
sc_out<int> out1; ++inc;
sc_out<int> out2; wait();
}
sc_signal<int> sig2;
int _internal;
void proc2();
SC_CTOR( my_module ) {
SC_THREAD( proc2 );
State
Stateofofinternal
internalvariables
variablesisispreserved
preserved=>
=>
sensitive << in2 << sig2;
} the
thevalue
valueofofinc
incisisincremented
incrementedby byone
one
}; each
eachtime
timethe
theprocess
processisisreactivated.
reactivated.
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Processes
½ Synchronous process SC_CTHREAD: o SC_METHOD

o SC_THREAD
½ Sensitive only to one edge of one and only one clock ã SC_CTHREAD
½ Called the active edge
½ Special case of a SC_THREAD process

½ Cannot use multiple clocks with a synchronous process
½ Triggered only at active edge of its clock

½ Therefore inputs are sampled only at the active edge.
½ It is not triggered if inputs other than the clock change.
½ Models the behavior of unregistered inputs and registered outputs
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Processes
½ Synchronous process SC_CTHREAD: o SC_METHOD

o SC_THREAD
½ Once invoked the statements execute until a wait() ã SC_CTHREAD
statement is encountered.
½ At the wait()statement, the process execution is suspended
½ At the next execution, process execution starts from the
statement after the wait()statement
½ Local variables defined in the process function are saved
each time the process is suspended.
Tip: Use wait(<pos_int>); to wait for multiple clock cycles.
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Processes
in1 o SC_METHOD
while (true) { o SC_THREAD
in1 out = in1 + in2; ã SC_CTHREAD
out
wait( );
in2 } out
in2
clock clock
in1 1 35 in1 1 35
in2 13 18 in2 13 18
out 14 out 14 53
SystemC 1.0.x SystemC 2.0
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Processes
o SC_METHOD
½ Synchronous Thread Process SC_CTHREAD: o SC_THREAD
ã SC_CTHREAD
½ Useful for high level synthesis.
½ Modeling of synchronous systems.
½ Modeling of sequential logic.
½ Models the behavior of a block with unregistered inputs and

registered outputs.
½ Useful for modeling drivers in test benches.
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Processes
SC_MODULE( my_module ) { void my_module::proc3() o SC_METHOD

o SC_THREAD
sc_in_clk clk; { ã SC_CTHREAD
sc_in<bool> reset_n; // start-up functionality goes here
int inc = 1;
sc_in<int> in1;
sc_in<int> in2; while(1) {
out2.write(inc);
sc_out<int> out1; sig2 = sig2 + inc;
sc_out<int> out2; ++inc;
wait();
int _internal;
void proc3();
SC_CTOR( my_module ) {
SC_CTHREAD( proc3, clk.pos() ); State
Stateofofinternal
internalvariables
variablesisispreserved
preserved=>
=>
} the
thevalue
valueofofinc
inc isisincremented
incrementedby byat
ateach
each
}; positive
positiveclock
clockedge.
edge.
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Unit Topic
2.1 Data Types
2.2 Processes
2.3 Hierarchy
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SC_MODULE
{
o Ports
½ Systems are modeled hierarchically o Signals
½ SystemC has to provide a mechanism for hierarchy o Variables
o Constructor
½ Solution o Processes
ã Modules
½ Modules may contain instances of other modules };
top
top
in a_in sub_a a_out b_in sub_b b_out out

sig
sub_a sub_b
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SC_MODULE(top)
SC_MODULE(top) SC_MODULE
{{ ½
½ Define
Define member
member variables
variables {
sc_in<int> for
for all
all the
the internal
internal signals
signals o Ports
sc_in<int> in;
in;
sc_out<int> that
that are needed to connect
are needed to connect o Signals
sc_out<int> out;
out;
the
the child
child module’s
module’s ports
ports to
to o Variables
each
each other.
other. o Constructor
sc_signal<int>
sc_signal<int> sig;
sig; o Processes
½
½ Note:
Note: aa port
port of
of the
the parent
parent ã Modules
sub_a*
sub_a* inst1;
inst1; module
module is directly bound to
is directly bound to };
sub_b*
sub_b* inst2;
inst2; aa port of the child module
port of the child module
....
.... (no
(no signal
signal needed).
needed).
};
};
top

sig
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SC_MODULE(top)
SC_MODULE(top) SC_MODULE
{{ ½
½ Define
Define member
member variables
variables {
sc_in<int> that
that are
are pointers
pointers to
to the
the o Ports
sc_in<int> in;
in;
sc_out<int> child
child module’s class for
module’s class for all
all o Signals
sc_out<int> out;
out;
instances
instances o Variables
o Constructor
sc_signal<int>
sc_signal<int> sig;
sig; o Processes
ã Modules
sub_a*
sub_a* inst1;
inst1; };
sub_b*
sub_b* inst2;
inst2;
....
....
};
};
top

sig
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SC_MODULE
½
½ Create
Create the
the child
child module
module {
SC_CTOR instances
instances within the
within the parent
parent o Ports
SC_CTOR {{
inst1 module’s
module’s constructor using
constructor using o Signals
inst1 == new
new sub_a("inst_1");
sub_a("inst_1");
the C++ keyword new.
the C++ keyword new. o Variables
inst2
inst2 == new
new sub_b("inst_2");
sub_b("inst_2"); o Constructor
½
½ An
An arbitrary
arbitrary name
name isis given
given o Processes
(*inst1).a_out(sig);
(*inst1).a_out(sig); to
to the
the module
module instances.
instances. ItIt ã Modules
(*inst1).a_in(in);
(*inst1).a_in(in); is
is good
good practice
practice to
to use
use the
the };
name of the instance
name of the instance
(*inst2)(sig,
(*inst2)(sig, b_out);
b_out); variable.
variable.
}}
top

sig
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SC_MODULE
½
½ Connect
Connect ports
ports of
of child
child {
SC_CTOR modules
modules to one another with
to one another with o Ports
SC_CTOR {{
inst1 internal signals.
internal signals. o Signals
inst1 == new
new sub_a("inst_1");
sub_a("inst_1");
o Variables
inst2
inst2 == new
new sub_b("inst_2");
sub_b("inst_2"); ½
½ Connect
Connect ports
ports of
of the
the parent
parent o Constructor
module
module to
to ports
ports of
of the
the child
child o Processes
(*inst1).a_out(sig);
(*inst1).a_out(sig); module
module using
using direct
direct port-to-
port-to- ã Modules
(*inst1).a_in(in);
(*inst1).a_in(in); port connection. A signal
port connection. A signal };
MUST
MUST NOT
NOT be
be used.
used.
(*inst2)(sig,
(*inst2)(sig, b_out);
b_out);
}}
½
½ Mapping
Mapping by
by name
name is
is
recommended.
recommended.
½
½ Mapping
Mapping by
by position
position may
may also
also
be
be used.
used.
top

sig
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Unit Topic
1 Why C-based Design Flow
4 Simple Example
5 Resources
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Software UTF Hardware
UTF ½ System/ Architectural Level
½not synthesizable
Refine ½event driven
½abstract communication
TF
TF ½abstract data types
Refine
½ Behavioral Level
Partition
½synthesizable
½clocked
Behavioral
Behavioral ½I/O cycle accurate
½algorithmic description
abstract Refine
abstract
RTOS
RTOS RTL
RTL ½ RT Level
Refine ½synthesizable
½clocked
target
target ½FSM
code Netlist
Netlist ½data path
code
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½ System/Architectural Level
½ channels, interfaces, events, master-slave comm. library (all beta)
½ Behavioral
½ synthesis to netlist
½ RTL
½ synthesis to netlist
½ Software
½ abstract RTOS (not yet available)
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½ Refine Structure
Functional Description
½ use signals for I/F
½ partition into synthesizable blocks
½ restrict to synthesizable language subset
½ Refine Control
½ specify throughput/latency Structure Control Data
½ specify I/O protocol
½ Refine Data
½ restrict to physically meaningful data
types (no abstract data)
½ specify bit width Implementable Description
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CPU
Clk
algorithmic driven
Bus IF
Clk
algorithmic driven I/O Board Disk
Bus IF
Clk Clk
driven algorithmic driven algorithmic
Memory Bus IF Bus IF
Clk
Bus driven
Arbiter Bus IF
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½Interface cycle accurate
½ ports and signals
½ synthesizable data types
½ introduction of a clock
SC_MODULE(fir) {
sc_in_clk clk; ½Rest of module
sc_in<bool> reset; ½ algorithmic
sc_in<T_DATA> in; ½ clocked (SC_CTHREAD)
sc_in<bool> in_data_valid;
½ restriction to synthesizable SystemC
sc_out<T_DATA> out;
sc_out<bool> out_data_valid; subset
...
SC_CTOR(fir) {
SC_CTHREAD(fir_process, clk.pos());
½Behavioral Code may utilize
... ½ functions to reduce code complexity
} ½ loops
};
½ conditional statements
½ no abstract data types for
ports/signals
½ only synthesizable subset of
SystemC
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CPU
CLK
driven
CLK I/O Board Disk

driven
Memory CLK
driven
Bus
Arbiter
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57/HYHO0RGHOLQJ0RGXOH
½Interface cycle accurate
½ ports and signals
SC_MODULE(fir) {
sc_in_clk clk; ½ synthesizable data types
sc_in<bool> reset; ½ introduction of a clock
sc_in<T_DATA> in;
sc_in<bool> in_data_valid;
sc_out<T_DATA> out; ½Rest of module
sc_out<bool> out_data_valid; ½ cycle accurate
... ½ sequential and combinational logic
sc_signal<T_STATE> state_curr, state_nxt;
... (SC_METHOD)
SC_CTOR(fir) { ½ restriction to synthesizable SystemC
SC_METHOD(fir); subset
sensitive << state_curr << in;
SC_METHOD(fsm);
sensitive << state_curr << data_valid; ½RTL Code may utilize
SC_METHOD(reg); ½ functions to reduce code complexity
sensitive_pos << clk;
sensitive << reset; ½ loops
... ½ conditional statements
} ½ no abstract data types for
};
ports/signals
½ only synthesizable subset of
SystemC IIS
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Unit Topic
4 Simple Example
5 Resources
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in1 in2
main.cpp
a1 in1
Stimulus Response
Adder out re
Generator Monitor
a2 in2
clk
+
stimgen.cpp
stimgen.cpp adder.cpp
adder.cpp monitor.cpp
monitor.cpp
stimgen.h
stimgen.h adder.h
adder.h monitor.h
monitor.h
out
main.cpp
main.cpp
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//
// header
header file
file adder.h
adder.h
typedef
typedef int
int T_ADD;
T_ADD; main.cpp
SC_MODULE(adder)
SC_MODULE(adder) {{ a1 in1
//
// Input
Input ports
ports Stimulus Response
sc_port<sc_fifo_in_if<T_ADD>
sc_port<sc_fifo_in_if<T_ADD> >> in1; Adder out re
in1; Generator Monitor
sc_port<sc_fifo_in_if<T_ADD>
sc_port<sc_fifo_in_if<T_ADD> >> in2;
in2;
a2 in2
//
// Output
Output ports
ports
sc_port<sc_fifo_out_if<T_ADD>
sc_port<sc_fifo_out_if<T_ADD> >> in2;
in2; clk
//
// Constructor
Constructor
SC_CTOR(adder){
SC_CTOR(adder){
SC_THREAD(main);
SC_THREAD(main);
}}
stimgen.cpp
monitor.cpp
//
// Functionality
Functionality of
of the
the process
process
void
void main();
main(); stimgen.h
stimgen.h adder.h
adder.h monitor.h
monitor.h
};
};
main.cpp
main.cpp
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main.cpp
a1 in1
Stimulus Response
//
// Implementation
Implementation file
file adder.cpp
adder.cpp Adder out re
Generator Monitor
#include
#include “systemc.h”
“systemc.h” a2 in2
#include
#include “adder.h”
“adder.h”
void
void adder::main()
adder::main() clk
{{
while
while (true)
(true) {{
out->write(in1->read()
out->write(in1->read() ++ in2->read());
in2->read());
//
// assign
assign aa run-time
run-time to
to process
process
wait(10,
wait(10, SC_NS);
SC_NS);
}} stimgen.cpp
monitor.cpp
}}
stimgen.h
stimgen.h adder.h
adder.h monitor.h
monitor.h
main.cpp
main.cpp
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// header file adder.h

main.cpp
typedef sc_int<8> T_ADD; a1 in1

Stimulus Response
Adder out re
SC_MODULE(adder) { Generator Monitor
// Clock introduced a2 in2
sc_in_clk clk;
// Input ports
sc_in<T_ADD> in1; clk
sc_in<T_ADD> in2;
// Output port
sc_out<T_ADD> out;
// Constructor stimgen.cpp
monitor.cpp
SC_CTOR(adder){
SC_CTHREAD(main, clk.pos());
stimgen.h
stimgen.h adder.h
adder.h monitor.h
monitor.h
}
// Functionality of the process

void main();
};
main.cpp
main.cpp
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main.cpp
// Implementation file adder.cc
#include “systemc.h” a1 in1
#include “adder.h” Stimulus Response
Adder out re
Generator Monitor
void adder::main()
{ a2 in2
// initialization
T_ADD __in1 = 0; clk
T_ADD __in2 = 0;
T_ADD __out = 0;
out.write(__out);
wait();
stimgen.cpp
monitor.cpp
// infinite loop
while(1) {
__in1 = in1.read(); stimgen.h
stimgen.h adder.h
adder.h monitor.h
monitor.h
__in2 = in2.read();
__out = __in1 + __in2;
out.write(__out);
wait();
} main.cpp
main.cpp
}
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// header file adder.h
typedef sc_int<8> T_ADD;

main.cpp
SC_MODULE(adder) {
// Clock introduced a1 in1
sc_in_clk clk; Stimulus Response
// Input ports Adder out re
Generator Monitor
sc_in<T_ADD> in1; a2 in2
sc_in<T_ADD> in2;
// Output port
sc_out<T_ADD> out; clk
// internal signal
sc_signal<T_ADD> sum;
// Constructor
stimgen.cpp
monitor.cpp
SC_CTOR(adder){
SC_METHOD(add);
sensitive << in1 << in2; stimgen.h
stimgen.h adder.h
adder.h monitor.h
monitor.h
SC_METHOD(reg);
sensitive_pos << clk;
}
// Functionality of the process

main.cpp
main.cpp
void add();
void reg();
};
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// Implementation file adder.cc
#include “systemc.h”
#include “adder.h”
void adder::add()
main.cpp
{
T_ADD __in1 = in1.read(); a1 in1
T_ADD __in2 = in2.read(); Stimulus Response
Adder out re
Generator Monitor
sum.write( __in1 + __in2 ); a2 in2
}
void adder::reg() clk

{
out.write( sum );
}
stimgen.cpp
monitor.cpp
stimgen.h
stimgen.h adder.h
adder.h monitor.h
monitor.h
main.cpp
main.cpp
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Unit Topic
4 Simple Example
5 Resources
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6\VWHP&:HE6LWH
www.systemc.org
½download
½news
½forum (mailing list)
½FAQs
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½ For SystemC training in Munich, Erlangen, or on-site

look at:
½ http://www.iis.fhg.de/kursbuch/kurse/systemc.html
½ Next scheduled training: Nov 21-23 in Munich,

Germany
Covers SystemC 2.0
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$Q,QWURGXFWLRQWR6\VWHP& [

½ This tutorial offers

½ This tutorial does not

2 Language Elements of SystemC

3 SystemC and Synthesis

Problems:Written specifications are incomplete and inconsistent

½ All these features are not supported by C++ as is IIS

class library debugger

2 Language Elements of SystemC

3 SystemC and Synthesis

2 Language Elements of SystemC

2.1 Data Types

2.1 Modules, Ports and Signals

½ SystemCTM provides other types that are needed for System

½use builtin C/C++ data types as much as possible

Fastest ½use sc_bigint/sc_biguint

2 Language Elements of SystemC

2.1 Data Types

2.1 Modules, Ports and Signals

(ending .h) clk

½ Module functionality in the

½ Module contains: stimgen.cpp algo.cpp monitor.cpp

½ Instances of other modules

Note: SC_MODULE is a macro for

½ Signals always carry a value

½ The usage of .read() and .write() avoids implicit type conversion,

½ initialize all data members of the module to a known state

Note: SC_CTOR is a macro for

2 Language Elements of SystemC

2.1 Data Types

2.1 Modules, Ports and Signals

½ Processes are not hierarchical

½ Processes use timing control statements to implement

½ Process and signal updates follow the evaluate-update

½ Processes are registered to the simulation kernel within the

½ Is invoked whenever any of the inputs it is sensitive to changes.

½ Model sequential logic

½ Monitor signals as part of a testbench

½ Use for RT level modeling

½ Model event driven systems (architectural level)

½ sensitive with stream notation (operator <<)

½ sensitive_pos with either () or << operator

½ sensitive_neg with either () or << operator

SC_CTOR( my_module ) { State

½ Is reactivated whenever any of the inputs it is sensitive to changes.

½ Asynchronous Thread Process SC_THREAD:

½ Most useful at higher levels of abstraction (esp. with SystemC 2.0)

½ Has to be replaced by asynchronous function or synchronous thread

½ May be used in test benches.

½ Implement synchronization and writing of signals in processes. o SC_METHOD

½ If no timing control statement used:

½ To write to an output signal, a process needs to invoke a timing

½ Multiple interacting synchronous processes must have at least

½ wait(<pos_int>) may be used to wait for a certain number of

½ In Synchronous process (SC_CTHREAD)

½ In Asynchronous process (SC_THREAD)

½ Synchronous process SC_CTHREAD: o SC_METHOD

½ Special case of a SC_THREAD process

½ Triggered only at active edge of its clock

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