A 20 GHz Low Noise Amplifier with Active Balun in a 0.
25 um SiGe
BICMOS technology
Brian Welch Kevin Kornegay
Comell University Comell University
330 Phillips Hall, Ithaca NY 14853 413 Phillips Hall, Ithaca NY 14853
bpwl@comelI.edu komegay@ece.cornell.edu
Abstract
A 20 GHz low nohe amplfler (LNA) with an active balun
Jabricated in a 0.25um SiGe BICMOS 6 = 47 GHz) rech-
nology is presented The LNA achieves 7 dE ofgain and a
noise figure of 4.9 dB with a// ports simultaneously
matched with better than -I6 dB ofrerum loss. The ampli-
Jer is highly linear wilh on IPIdB of0 dEm ond IIP3 of9
dEm, while consuming 14 mA OJDC current Jrom a 3 . 3 ~
rail. Ta the authors knowledge fhe LNA delivers the lowesr
reported noise figure and highest lineariry for o silicon
implemenralion oJan (active balun/LNA) a1 20 GHz.
INTRODUCTION
With the increasing demand for wireless communications, a
need has evolved to provide data transfer rates beyond
those capable with current cellular standards. Advance-
ments in silicon technologies are making RF applications
above 20 GHz increasingly viable regarding both cost and
integration capabilities. This progress makes possible the
integration of an entire microwavelmillimeter-wavetrans-
ceiver on a single IC, and quells the need for employing
expensive multi-chip systems implemented using more
exotic technologies. Recent work in this arena has been
performed using 0.18 p~ (and below) CMOS and SiGe
BiCMOS technologies, however this is the first known 20
GHz circuit realization using a 0.25 Fm SiGe BiCMOS
technology [I-$]. The purpose of this work is to achieve a
high operating frequency in a low A technology (47 GHz),
with reasonable noise, gain, and linearity.
1
Figure 1: Simplified LNA Schematic
a2004 IEEE.
07803-86167/04/$20.W 141
Hyun-Min Park, Joy
Laskar
Georgia Institute of Technology
School of ECE. Atlanta GA 30332
joy.lascar@ece.gatech.edu
LNA Design
A simplified schematic of the three stage LNA is shown in
figure I . The input stage is a single-ended common-emitter
amplifier with a voltage bias applied at the base. Device
area is minimized to provide optimum noise figure while
still providing a high gain. Input matching is achieved with
a small emitter degeneration inductor Le1 , and the resonant
circuit created by the inductor Lbl and the dc blocking cap
Cbl. Here the input impedance can be expressed as [ 5 ] :
-
Where g. is the transistor transconductance and rb is the
base resistance. The second stage is an emitter coupled pair
---~
_-
degenerated with an LC tank (created by Le2 and Cel)
optimized to resonate at twice the operating frequency (40
GHz) to reject the common mode at the emitters. Ignoring
the effect of the differential half of the pair the input im-
pedance of the second stage can be written as:
The second stage also has a voltage bias applied across the
base of each transistor and is ac coupled to the first stage
with capacitor Cb2, which resonates with inductors Lcl,
Lb2, and Lb3 to achieve a 50 Q interstage match. The two
matching inductors are of different size to compensate for
the lack of loading on the differential branch due to the
input stage, which allows them to operate 180" out of
phase.
Output matching is achieved with the inductors Lc2 and
Lc3, which are dc coupled to a pair of emitter followers.
These emitter followers are used to transform a high collec-
tor impedance at the outputs of the emitter coupled pairs
into a low output impedance at the emitters of the two fol-
lowers, which is matched to 50 Q by inductors Le4 and Le5
and dc blocking capacitors Ce4 and Ce5.
The second and third stages were laid out symmemcally
about the horizontal axis to ensure comparable parasitic
effects (with the exception of variations in size of the
matching inductors Lb2 and Lb3). Strait wire inductors
were used to allow for large spacing between the inductors
for better isolation. All inductors were shielded at a dis-
2004 IEEE CSIC Digest
 tance of no less than 80 pm with a ground line to provide a
local current return path. lnterstage 50 R transmission lines
were used to minimize the amount of non-modeled wiring,
and banks.of decoupling capacitors were located at the ter-
mination of each inductor (and the collectors of the two
emitter followers) to provide good local ac return paths (50
Cl pads and wiring were also used in the test environment
to eliminate a potentially highly inductive power network).
Figure 2: Small Signal Measurements
.=-
-
.-
Experimental Results
The LNA was measured unpackaged, using Cascade Mi-
crotec wafer probes. Single ended measurements were per-
formed with the unused output port terminated into 50 n.
This was done for both output port 2 and port 3, for both
small signal and noise figure measurements. Power meas-
urements were only measured for output port 2. Biasing
was provided using 50 R G-S-G-S-G probes (150 pm
pitch), with each bias network containing its own Vdd pin
to enable independent tuning of each stage (although each
was tested at 3.3~). 100 pm G-S-G-S-G probes were used
for both the input and output, with the unused input pad left
floating. Deembedding was performed using Cascade Mi-
crotec alumina standards.
Figure 2 shows the small signal S-parameters for the LNA
with active balun, where S21 is 6.3 dB and S31 is 6.7 dB at
20.5 GHz. These measurements indicate better than -16 dB
of retum loss at the input port and bener than -26 dB of
retum loss at each of the output ports.
- "I-
-
-I,
Figure 3: Measured and Simulated Feed-forward Phase
In Figure 3 there is a 40" disparity in the simulated and
measured results for the output phases of the two paths.
142
Since only single-ended measurements were possible and
each set of small signal data relied on a different calibration
(the output port connection had to be moved between the
two signal pads of the G-S-G-S-G, requiring the probes to
be removed from the IC), exact phase testing was not pos-
sible. Considering that the wavelength at 20 GHz is not an
insignificant portion of the length of these pads (100 pm),
the electrical length of the inputioutput wires can be largely
dependent on whether the probe makes contact at the front
or back of the pad. Without having access to a four-port
network analyzer achieving a highly accurate phase meas-
urement would be difficult, but even without extracting the
exact phase measurements it can be seen that this topology
is suficient for creating two distinct and separate phases.
V,..".".. ,e*.,
Figure 4 Measured and Simulated Noise Figure
Measured and simulated noise figures of the LNA are
shown in Figure 4. At 20.5 GHz output port 2 yields a noise
figure of 4.89 dB while output port 3 yields a noise figure
of 5.91 dB. The noise figure of output port 2 is the lowest
known value at 20 GHz for a silicon LNA. The simulated
noise figures are included to show the general shape of the
curves (some rippling introduced during testing), and to
emphasize that the difference between the noise figures
(ports 2 & 3) remained at about 1 dB (showing that the
symmetrical layout style introduced the same parasitic ef-
fects to each path).
" . ,. I, * . 1 . .
--I
Figure 5 Input Referred 1dB Compression Point
 Conclusion
A 20 GHz LNA with active balun on silicon for use in a
microwave receiver has been presented. The circuit em-
ploys a common-emitter input stage and emitter coupled
balun stage to achieve low noise, and excellent matching &
fi linearity. In table 1 we show that this LNA achieves a
lower noise figure than other comparable Silicon LNA’s in
the 20 GHz range, while acting as an active balun, which
eliminates the need for a noisy passive balun. A summary
of the LNA performance results is given in table 2.
Table 2: LNA Performance Summary
Figure 6: Input Referred IP3
Figures 5 and 6 indicate that the LNA is highly linear, with
an input referred IdB compression point of 0 dBm and in
input referred IP3 of 9 dBm (extrapolated fiom -5 dBm
input power). These measurements were observed while
drawing 14 mA of current from a 3.3 V rail, for a total
power consumption of 46.2 mW. The chip microphoto-
graph is shown in Figure 7.

This work demonstrates that circuits designed for 20 GHz

operation are possible using silicon technologies, even
without drastic reduction of the minimum feature size. This
demonstration was achieved at nearly half the available f,
of the technology, with minimal performance differences as
compared to circuits at a quarter of its fiequency [6,7].

ACKNOWLEDGMENTS
The authors would like to thank MOSS for fabrication
under the MOSS educational program, Qualcomm for par-
tial funding of this work, and John S. Duster and the Geor-
gia Institute of Technology for testing support.

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Feature Technology Balun Frequency Gain NF
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LNA in [2] 0.10 prn (A =95 GHz) sol NO 23.8 GHz 1.3 dB IO dB
LNA in [31 0.18 prn Bulk SI NO 24 GHz 15 dB 6 dB
This Work 0.25 pm ( F A 7 GHz) SiGe Yes 20.5 GH2 6.9 dB 4.89 dB

143
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