Metal Oxide Semiconductor

Field Effect Transistor (MOSFET)

Structure:
S G D
metal oxide

n n
semiconductor
p+

1
 MOSFET operation

If VG=0 Assuming VD=high, VS=0

G
S D

n No current nn

p+

2
 MOSFET operation

If VG=high Now if VD=high, there is a current

flow between D and S
G
S D

++ ++

n nn
Gate voltage attracts
electrons and pushes
holes away
An n type channel
is formed
p+

3
 MOSFET structures and circuit symbols

Depl et i on r egi on
Gate
Sour ce Dr ai n
+
n n+ Dr ai n Dr ai n Dr ai n
Si O2

Gate
Bul k
p- t ype subst r at e

Sour ce Sour ce Sour ce

Channel Subst r ate

(a) (b) (c) (d)

(a) Schematic structure of n-channel MOSFET (NMOS) and

circuit symbols for (b) MOSFET, (c) n-channel MOSFET, and (d)
n-channel MOSFET when the bulk (substrate) potential has to
be specified in a circuit.

4
 Complementary MOSFET pairs

Gat e n- channel p- channel

Sour c e Dr ai n

+ Dr ai n Dr ai n
+ Si O2 Si O2 p
n

Gat e

n- t y p e wel l Bul k
p- t yp e subst r at e

Sour ce Sour c e
Subst r at e

Schematic structure of Complementary MOSFET (CMOS) and

circuit symbols for p-channel MOSFET (PMOS). Minuses and
pluses show the depletion regions.

5
 Sub-threshold mode of MOSFET operation

• VG = 0; the MOSFET conducting channel

V =0
is not formed G

higher V Channel G
Energy

Ec ²E F2
²E F1
Source
ΦB Drain

EF

Distance

In the subthreshold regime, the MOSFET current is a small reverse current

through the source – substrate and drain – substrate p-n junctions;
Only a small number of electrons can pass over the potential barrier
separating the drain and the source.

nST ≈ nSource × e − ( Φ B / kT )
6
 Sub-threshold mode of MOSFET operation
10 2
V ds = 3.0 V
0
VG1 10

-2 It 0.05 V
10
VG2
-4
10

VG3 10 -6
Source Drain -8
10
VG1<VG2<VG3
-10
10
-0.2 0.2 0.6 1.0 1.4 1.8
Gate-source voltage (V)

In the sub-threshold regime, the channel current is very low and increases
exponentially with the gate bias.

nST ≈ nSource × e − ( Φ B / kT )
7
 MOSFET threshold voltage
VG1<VG2<VG3 10 2
V ds = 3.0 V
VG1 10
0

-2 It 0.05 V
VG2 10

-4
10
VG3
10 -6
Source Drain -8
10
VT -10
10
-0.2 0.2 0.6 1.0 1.4 1.8
Gate-source voltage (V)
At certain gate bias called the threshold voltage, the conductivity type under
the gate inverts and the barrier between the Source and the Drain
disappears.
Electrons can enter the region under the gate to form a
conducting n-channel.
At the gate voltages above the threshold, the gate and the channel form a
Metal-Insulator-Semiconductor (MIS) capacitor.
8
 MOSFET above the threshold voltage
The free electron charge in the MOSFET channel (per unit area):

Q1 = CGATE × (VG – VT)

(assuming that at VG = VT the free electron concentration is zero)

In MOSFETs, the gate and channel form a MIS-capacitor,

hence the capacitance per unit gate area

ci = ε i / d i = ε ir ε 0 / d i
εi = εir ε0 is the total dielectric permittivity of the gate dielectric
(usually, SiO2), εir is the relative dielectric permittivity of the gate dielectric.

Total gate capacitance CG = ci ×A, where A is the gate area

The sheet electron concentration above the threshold, nS is given by:

qns = ci (VGS − VT ) = ci VGT

9
 MOSFET above the threshold voltage
10 2
V ds = 3.0 V
0
10

-2 It 0.05 V
10

-4
10

10 -6

-8
10

-10
10
-0.2 0.2 0.6 1.0 1.4 1.8

qns = ci (VGS − VT ) = ci VGT Gate-source voltage (V)

Above the threshold, the sheet electron concentration and hence

the channel current increase linearly with the gate bias VG.

10
 MOSFET Threshold Voltage
S G D
metal oxide

n n
semiconductor
p+

Source Drain

11
 Band Diagram at the MOS interfaces
Before Contact

Vacuum level
oxide
q χox
EC
n
qφm q χs qφs

EC

EFm
Ei
p+ Eg EFs
EV

metal
n
EV

METAL OXIDE SEMICONDUCTOR 12

After Contact Metal and semiconductor Fermi levels align by
electron transfer. Bending is the result of the
presence of transferred electron

E
ECC

n EC

EC
Ei
EFm EFs
EVEi
EFs
p+ EV

n EV

METAL OXIDE SEMICONDUCTOR

13
 n
Flat band Voltage

VG
p Gate voltage making the band flat
+ VFB= φm-φs
n
EC

EC EC
EC
EC EFm EC
EFm
Ei
Ei VG EFs VG Ei
EFs EV EFs
VG EV EV

EFm

EV
EV EV
VG=VFB
VG>0 VG<VFB
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 Conductivity conversion in MOSFET

n n

VG Less holes at the

VG interface, more
p p
bending
+ +

n n

Less p type p type

EC
EC

Ei
Ei
EFs
EFs
EV
EV

VG ↑
VG=0 More depletion 15
 n n

VG VG
p p
+ +
n n

Less p type p type Less p type p type

EC EC

Onset of
Channel Ei Channel Ei
creation EFs created EFs

EV EV

VG ↑ ↑ VG ↑ ↑ ↑
n type Inversion n type Strong Inversion
16
 Inversion condition in MOSFET
Equilibrium hole concentration in the bulk of semiconductor
qφb EC

p = ni e kT
Ei
qφb is the Fermi level offset from qVs qφb EFs
the mid-gap in the bulk material
EV

Surface potential Vs
is controlled by the gate voltage

Accumulation Depletion Onset of inversion Inversion

Vs<0 Vs<φb Vs=φb Vs>φb

Strong Inversion When Vs = 2φb, n-concentration at the surface

is the same as p-concentration in the bulk
Vs>2φb
17
Surface potential required to reach
the MOSFET threshold

qφb qφb
n = ni e kT p = ni e kT
EC

Ei
φb
VsT=2φb EFs
φb
EV

When Vs = 2φb, n-concentration at the surface

is the same as p-concentration in the bulk

18
 Surface potential and gate voltage
• VG is the gate voltage, as source is grounded, EC
Vi
VG=VGS EC
• Vi is the voltage drop across the oxide/insulator
Ei
Vs
• Vs is the surface potential EFs
VG EV

EFm

VGS = VFB + Vs + Vi
EV

19
 Voltage drop across the oxide layer
VGS = VFB + Vs + Vi Vi
EC

EC

Vi is the voltage drop across the oxide/insulator Ei

Vs
EFs
Gate electrode and semiconductor form the VG EV

plates of the MOS capacitor. EFm

Voltage drop across the capacitor:

Q
Vi = d
Ci EV

where Qd is the capacitor charge and Ci is the capacitance.

Since the charges on the metal and semiconductor plates are the same,
Qd can be calculated as the charge in semiconductor.
The semiconductor charge is formed by the charge of the depletion region

20
 Voltage drop across the oxide layer
EC
The relation between the depletion region width W and Vi
EC
the applied voltage Vs:

q Na W 2 Ei
Vs =
Vs
EFs

2εs VG EV

2εVs EFm
Form this, W=
qN a
EV

The depletion region charge (per unit area):

2εVs
Qd = qN a W = qN a
qN a
→ Qd = 2ε s qN aVs

21
 Voltage drop across the oxide layer
EC
Q Vi
Vi = d
ci EC

where, Qd = 2εs qN a Vs Vs
Ei
EFs
VG EV

is the depletion region charge per unit area, EFm

ci is the MOS-capacitor capacitance per unit area:

εi
ci = EV
di

di is the thickness of the oxide film under the gate

22
 MOSFET threshold voltage (cont.)
The MOSFET threshold voltage is defined as the Gate
voltage leading to the strong inversion, i.e. Vs = 2φb
2ε s qN aVs
VGS = VFB + Vs +
ci
At the onset of strong inversion:

2ε s qN a ( 2φb )
VT = VFB + ( 2φb ) +
ci

Finally, the threshold voltage,

VT = VFB + 2ϕb + γ 2ϕb

N

where the body effect constant, γ N = 2ε s qN a / ci

23
 Effect of Body Bias

VS VG
VD

n n

p+

VBS ≠0

the Threshold voltage,

VT = VFB + 2ϕb + γ N (2ϕb − VBS )

24
 Effect of Surface States
VS VG During the oxide growth on Si, dangling
VD
bonds are created that contributes to
wanted trapped charges at the interface

n n
++++++++++
p+

VBS ≠0

the Threshold voltage,

VT = VFB +
Q ss
Ci
+ 2ϕ b + γ N (2ϕb − VBS )

Qss : surface state charges per unit area

25