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Always Blocks
Always Blocks
Always Blocks
always_comb begin
unique case ( done_sm_ps )
NOT_DONE :
begin
done = 1 ’ b0 ; // not done indication
if (( cycle_cnt ==5 ’ d31 )&
( mult_sm_ps == SHIFT )) done_sm_ns = DONE ;
else done_sm_ns = NOT_DONE ;
end
DONE :
begin
done = 1 ’ b1 ; // indicate done
done_sm_ns = NOT_DONE ; // go back
end
endcase
end
always blocks
I Note that:
I always comb used the blocking ”=” assignment
I Use blocking assignments in always blocks that are written to
generate combinational logic.
I always ff used the non-blocking ”<=” assignment
I Use nonblocking assignments in always blocks that are written to
generate sequential logic.
I Ignoring these guidelines may infer correct logic gates, but
pre-synthesis simulation might not match the behavior of the
synthesized circuit.
1
”Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill!, Clifford
E. Cummings, Sunburst Design, Inc., SNUG-2000, San Jose, CA”
always blocks
I It is also often used to denote a fill value. In other words it lets you
set all the bits of a vector to a value without specifying radix or size.
data = ’1; // set all the bits of data to V_dd }
if ( rst ) y1 <= ’0; // set all bits of y1 to V_ss ( ground )