TN 423: VLSI CIRCUITS

Lecture 6c

CMOS IC DESIGN CONSIDERATIONS

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 Outline
Ω Layout Design Rules

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 Layout Design Rules
Layout
Circuit
Designer
Designer

Si CMOS CMOS ntwk Sticks Layout

PMOS PUP Layer Design

Fabrication represent
NMOS PDN ation Rules

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 Layout Design Rules
Ω The physical layout of any circuit that has to be
fabricated using any process (nMOS, pMOS, CMOS)
must satisfy a set of geometric rules known as design
rules
Ω Design rules allow a ready translation of circuit design
concepts in stick diagram or symbolic form into actual
geometry in silicon
Design Rules

Actual
Circuit Designed in Geometry in Si
Stick Diagrams

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 Layout Design Rules
Ω These are a set of guidelines that specify the
minimum dimensions and spacing allowed in a
layout drawing
Ω Violating a design rule might result in a non-
functional circuit
Ω The design rules can be expressed as a list of
minimum features and spacing for all the masks
required in a given process

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 Layout Design Rules

Minimum line-width
Smallest dimension
permitted for any object in
the layout drawing
Minimum spacing
Smallest distance permitted
between the edges of two
objects

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 Layout Design Rules
Ω Design rules define a range of features:
 Minimum wire width to avoid breaks
 Minimum spacing to avoid shorts
 Minimum overlap to ensure complete overlaps
 Resolution/torelance of masks
Ω Fabrication processes are defined by
 the minimum channel width
 How fast a fabrication process is

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 Layout Design Rules
Ω Design rules are the interface between the
circuit designer and the fabrication engineer
Ω Circuit designers want lighter, smaller layouts
for
 Improved performance and
 high packing density
Ω Layout design rules describe
 how small features can be shown on the layout
 how closely they can be reliably packed in a
particular manufacturing process.

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 Layout Design Rules
Ω Industrial design rules are usually specified in
microns.
Ω This makes migrating from one process to a
more advanced process or a different foundry’s
process difficult because not all rules scale in
the same way.

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 Layout Design Rules
Ω Process engineer wants design rules that result in
controllable and reproducible process
Ω These design rules specify the min allowable line
widths for physical objects
Ω design rules are based on a single parameter, λ,
that characterizes the resolution of the process.
Ω λ is generally half of the minimum drawn transistor
channel length.
Ω This length is the distance between the source and
drain of a transistor and is set by the minimum
width of a polysilicon wire.

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 Layout Design Rules
Ω The layout design rules represent a reasonable
optimum point in terms of yield, reliability and
density
Ω These rules significantly increase the probability
of fabricating a successful product with high
yield
Ω There are two types of design rules
 Micron rule
 Lambda rule

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 Layout Design Rules
1. Micron (μ) rule
Ω All minimum sizes and spacings are stated in terms of
in micrometers (μm) =10-6m
Ω Sizes are expressed in terms of absolute (fixed)
dimensions
Ω No scaling is allowed
Ω List of minimum feature sizes and spacing for all masks
 Micron rules can result in as much as a 50% size
reduction over lambda rules.
 Normal style for industry.

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 Layout Design Rules
2. Lambda (λ) rule
Ω All minimum sizes and spacings are stated in terms of a
single parameter lambda (λ)
Ω Lambda (λ) is given by:
λ=l l =2λ; where l =channel length
Ω Lambda rules allow linear, proportional scaling of all
geometrical constraints
Ω Minimum line width: 2λ
Ω Main disadvantages:
 Limited linear scaling
 Too conservative

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 Layout Design Rules
Ω Example:
Ω For a transistor with l = 180 nm process has a
minimum polysilicon width l =0.18μm
By Lambda design rule,
λ l/2 = 0.18/2μm =0.09μm
lambda-based rules actually set λ= 0.10 μm,
Ω then shrink the gate and drain by 10 nm while
generating masks

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 Layout Design Rules
Ω λ based design rules were designed to simplify
the industry std micron rules to allow scaling
capability for various processes
Ω Lambda rules are based on the work by Mead
and Conway
Ω The simplicity of λ rules provides introduction to
design rules and to mask layout design
Ω It provides a process and feature-size
independent way of setting out mask
dimensions to scale

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 Layout Design Rules
Ω Lambda-based rules are necessarily
conservative because they round up
dimensions to an integer multiple of λ

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 Layout Design Rules
Design Rule Entities
1. Layer Representations
 Substrates and/or Wells
 Diffusion Regions (Active areas)
• Select regions: For contacts to substrate or well
 Polysilicon Layers
 Metal Interconnects
• Contact: Metal to active
• Via: Metal to metal
2. Intralayer Constraints
3. Interlayer Constraints

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 Layout Design Rules
Layer λ rule μ rule

N-well layer
Minimum size 10λ 2μ
Minimum spacing (wells at the 6λ 2μ
same potential)

Minimum spacing (wells at 8λ 2μ

different potential)

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 Layout Design Rules
Ω N-well

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 Layout Design Rules

λ rule μ rule
Polysilicon layer
Minimum size 2λ 1μ
Minimum spacing 2λ 1μ
Spacing to Active Area 2λ 0.5μ

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 Layout Design Rules

λ rule μ rule
Metal 1
Minimum size 3λ 1μ
Minimum 3λ 1μ
Spacing
Metal 2
Minimum size 3λ 1μ
Minimum 3λ 1μ
Spacing

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Layout Design Rules

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 Layout Design Rules

Contact
Minimum size 2λ 0.75μ
Minimum spacing 2λ 1μ
Minimum overlap 2λ 0.75μ

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 Layout Design Rules
Via
Minimum Size 2λ 1μ
Minimum spacing 3λ 1.5μ

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 Pitch and Spacing
Ω Design rules define:
 the minimum widths of wires and vias,
 the minimum wire-to-wire spacing, and
 the minimum via-to-via spacing of a layer.
Ω The distance between two wires or routing
tracks of the grid-based model is often called
wire pitch.
Ω Other design rules of the manufacturing
process, such as resistance and capacitance of
each layer, are also included

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Pitch and Spacing

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 Pitch and Spacing
Ω Routing track is the space required to place a
wire and the required spacing to the next wire.
Ω If our wires have a width of 4λ and a spacing of
4λ to the next wire, the track pitch is 8λ (4+4)

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 Pitch and Spacing
Ω This pitch also leaves room for a transistor to be
placed between the wires

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 Height and width of a cell
Ω It is reasonable to estimate the height and width
of a cell by counting the number of metal tracks
and multiplying by 8λ

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 Height and width of a cell
Ω Estimating the size of a 3-input NAND.
 There are four vertical wire tracks, multiplied
by 8λ per track to give a cell width of (8λ x4)
32λ.
 There are five horizontal wire tracks, giving a
cell height of (8λ x5) 40λ.
 Even though the horizontal tracks are not
drawn to scale, they are still easy to count

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 Wiring Tracks
Ω A wiring track is the space required for a wire
 4  width, 4  spacing from neighbor = 8  pitch
Ω A Transistor consumes one wiring track

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 Well spacing
Ω Wells must surround transistors by 6 
 Implies 12  between opposite transistor flavors
 Leaves room for one wire track

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 Area Estimation
Ω The area is estimated by counting the
number of wiring tracks
 Multiply by 8 to express in 

(height)

(width)
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 Questions

Question 1:
• Given the cell
shown on the
right, find the
– Height
– Width and
– area of the cell

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 Questions

Question 2:
•Given the cell shown
on the right, find the
following:
i. Length
ii. Width
iii. Area

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