A First Look at ARM Instruction Set Architecture

EE 3323: Spring 2019

Load Store Architecture

Basic components of a computer are shown in Figure 1. All code and data are stored in Memory (Von
Neumann architecture). ALU is the part which is responsible for all the computations like addition, sub-
traction, multiplication, comparisons and other logical operations. In this simplified model ALU does not
communicate directly with memory. But data from memory is first copied to general purpose registers.
ALU performs operations on operands available in the registers. Such an architecture is called load store
architecture.

Figure 1: Basic Computer Architecture

In this handout we focus on the instruction set for ARM processors. The instruction set is similar to a
typical RISC ISA. RISC stands for Reduced Instruction Set Computer. Such an ISA has very small number
of instruction types and formats and is easier to learn and understand. We start with this type of ISA
because we want to first focus on understanding the basic concepts of assembly language without worrying
too much about syntax details. Once we have solidified our understanding, we’ll move to actual syntax
details of 8086 architecture in a few lectures. So lets begin with our simple ARM ISA.

Registers
Our ARM processor has 16 registers, each of which can hold a 4-byte word. Out of these registers 13 registers
(R0 to R12) are general purpose registers i.e., they are used for manipulating data. The remaining three are
special purpose register.
• R13 (Stack Pointer or SP): Holds address of the top of the stack

• R14 (Link Register or LR): Holds return address from subroutine

• R15 (Program Counter or PC): Hold address of the next instruction to be executed
In addition to these registers, there is another register which is called Processor Status Register or PSR.
This register holds condition code flags (N, Z, C, V) and some other control information. We’ll concern with
only the condition code flags at the moment, as they are used in implementation of branch instructions.

Instructions
We will support three types of instructions: Load/Store instructions which move bytes back and forth be-
tween registers and memory, ALU instructions which operate on the registers, and Branch/Jump instructions
that alter which instruction is executed next.

1
Load Operation
Load instructions read bytes into a register. The source may be a constant value, another register, or a
location in memory. In our simple language, a memory location is expressed Mem[address] where address
may be a constant number, a register, or a register plus a constant offset. Load and Store normally move
a whole word at a time starting at the given address. To move less than a whole word at a time, use the
variants LDRBB (1 byte) LDRH (2 bytes). See the following examples:

1. Load constant 12 into register 2

MOV R2,#12
2. Copy contents of register 2 into register 3
MOV R3, R2
3. Load R5 with the word whose memory address is in R1
LDR R5, [R1]
4. Load the word that begins 8 bytes after the address in R1. This is known as ”constant offset” mode.
LDR R4, [R1, #8]

Store Operation
Store instructions are basically the reverse of load instructions they move values from registers back out
to memory. There is no path in a RISC architecture to move bytes directly from one place in memory to
somewhere else in memory. Instead, you need to use loads to get bytes into registers, and then stores to
move them back to memory. Following examples show the use of store instruction:

1. Store the constant number 37 into the word beginning at address 400
MOV R0, #37;
MOV R1, #400;
STR R0, [R1]

2. Store the value in R6 into the word whose address is in R1

STR R6, [R1]
3. Store lower half-word from R2 into 2 bytes starting at address 124
MOV R1, #124
STRH R2, [R1]
4. Store R7 into the word whose address is 12 more than the address in R1
STR R7, [R1,#12]

ALU
Arithmetic Logical Unit (ALU) instructions are much like the operation keys of a calculator. ALU operations
only work with the registers or constants. Some processors don’t even allow constants (i.e. you would need
to load the constant into a register first).
1. Add 6 to R3 and store the result in R1. (Note: only last operand can be a constant)
ADD R1, R3, #6
2. Subtract R3 from R2 and store the result in R1
SUB R1, R2, R3

2
Branching
By default, the CPU fetches and executes instructions from memory in order, working from low memory to
high. Branch instructions alter this default order. Branch instructions test a condition and possibly change
which instruction should be executed next by changing the value of the PC register. One condition that all
processors make heavy use of is testing whether two values are equal or if a value is less (or greater) than
some other value. Branch instructions in the ARM ISA rely on the condition code flags. Usually, these
condition code flags are set by a compare instructions. The compare instruction CMP R1, R2 performs the
operation R1 - R2 and sets the condition code flags based on the result of the subtraction operation. The
result itself is discarded.
Branches are used to implement control structures like if and switch as well as loops like for and while.
1. Begin executing at label next if R1 equals 0
CMP R1, #0;
BEQ next ;
Full set of branch instructions is as under:
1. BLT: branch if first argument is less than second
2. BLE: less than or equal
3. BGT: greater than
4. BGE: greater than or equal
5. BEQ: equal
6. BNE: not equal
7. BAL: always

Summary
Although there are a few things we bypassed (the logical and/or/not and some of the operations that support
function call/return), this simple set of instructions gives you a pretty good idea of exactly what our average
CPU can do in terms of instructions. The richness and complexity of a programming language like C is
provided by the compiler which takes something complex like a for-loop, array reference, or function call and
translates it into an appropriate sequence of the above simple instructions.