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Use System Verilog "Always Comb" Use Blocking Assignment Only System Verilog Always Comb Infers Sensitivity List Always - Comb If (A) Z X Else Z y
Use System Verilog "Always Comb" Use Blocking Assignment Only System Verilog Always Comb Infers Sensitivity List Always - Comb If (A) Z X Else Z y
- Always Block
always_comb
if(a)
z = x;
else
z = y;
What did we forget? - Always Block
I Counters and shift regs are coded differently from state machines
I Mixed combo logic and flip-flops under always ff clause
//simple counter
always_ff @ (posedge clk, negedge reset_n)
if(~reset_n) q_out <= 0;
else if(en) q_out <= q_out + 1;
What did we forget? - State Machines
I Do it like this!
always_comb begin
module arbiter0( arbiter_ns = XX; //default, ns vector
output reg gnt, gnt = 1’b0; //default, output signal
input clk, //clock input case (arbiter_ps)
input rst_n, //asynchronous active low reset IDLE :
input dly, //delay input if (req) arbiter_ns = BBUSY;
input done, //done input else arbiter_ns = IDLE;
input req //request input BBUSY: begin
); gnt = 1’b1; //assert gnt
if (!done) arbiter_ns = BBUSY;
//define enumerated types and vectors for ps, ns else if ( dly) arbiter_ns = BWAIT;
enum reg [1:0]{ else arbiter_ns = BFREE;
IDLE = 2’b00, end
BBUSY = 2’b01, BWAIT: begin
BWAIT = 2’b10, gnt = 1’b1; //assert gnt
BFREE = 2’b11, if (!dly) arbiter_ns = BFREE;
XX = ’x } arbiter_ps, arbiter_ns; else arbiter_ns = BWAIT;
end
//infer the present state vector flip flops BFREE:
always_ff @(posedge clk, negedge rst_n) if (req) arbiter_ns = BBUSY;
if (!rst_n) arbiter_ps <= IDLE; else arbiter_ns = IDLE;
else arbiter_ps <= arbiter_ns; endcase
end //always
endmodule
What did we forget? - Coding