Códigos utilizados

Registro de corrimiento de 4 bits

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity reg_corri_4b is
Port ( clk,load,en : in STD_LOGIC;
p_in : in STD_LOGIC_VECTOR (3 downto 0);
s_out : out STD_LOGIC);
end reg_corri_4b;

architecture Behavioral of reg_corri_4b is

signal registro: std_logic_vector(3 downto 0);

begin
process(clk)
begin
if rising_edge(clk)
then if load ='1'
then registro <= p_in;
s_out<='0';
elsif en='1'
then registro <= registro(2 downto 0) & '0';
s_out<= registro(3);
end if;
end if;
end process;
end Behavioral;

Corrimiento de 12 bits

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity reg_12b is
Port ( clk,en,clr : in STD_LOGIC;
dato_in : in STD_LOGIC_VECTOR (11 downto 0);
dato_out : out STD_LOGIC_VECTOR (11 downto 0));
end reg_12b;

architecture Behavioral of reg_12b is

begin

process(clk)
 begin
if rising_edge(clk)
then if clr='1'
then dato_out <=(others =>'0');
elsif en ='1'
then dato_out <= dato_in;
end if;
end if;
end process;
end Behavioral;

Multiplexor

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux is
Port ( a,b : in STD_LOGIC_VECTOR (11 downto 0);
sel : in STD_LOGIC;
z : out STD_LOGIC_VECTOR (11 downto 0));
end mux;

architecture Behavioral of mux is

begin

z<= a when sel='0' else b;

end Behavioral;

Sumador

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity sumador is
Port ( a : in STD_LOGIC_VECTOR (11 downto 0);
b : in STD_LOGIC_VECTOR (7 downto 0);
z : out STD_LOGIC_VECTOR (11 downto 0));
end sumador;

architecture Behavioral of sumador is

begin
 z<= a + ("0000"&b);

end Behavioral;

Registro de 8 bits

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity reg_8b is
Port ( clk,en: in STD_LOGIC;
dato_in : in STD_LOGIC_VECTOR (7 downto 0);
dato_out : out STD_LOGIC_VECTOR (7 downto 0));
end reg_8b;

architecture Behavioral of reg_8b is

begin

process(clk)
begin
if rising_edge(clk)
then if en ='1'
then dato_out <= dato_in;
end if;
end if;
end process;
end Behavioral;

Contador

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity contador is
Port ( clk,load,en : in STD_LOGIC;
fin_cnt : out STD_LOGIC);
end contador;

architecture Behavioral of contador is

signal cont: integer range 4 downto 0;
begin
process(clk)
begin
 if rising_edge(clk)
then if load ='1'
then cont<=4;
elsif en='1'
then if cont>0
then cont<=cont-1;
end if;
end if;
end if;
end process;

fin_cnt<='0' when cont>0 else '1';

end Behavioral;

Máquina de estado

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity M_Estado is
Port ( clk, reset, start, fin : in STD_LOGIC;
alfa,beta,gama : out STD_LOGIC);
end M_Estado;

architecture Behavioral of M_Estado is

type estados is (espera, inicia, desplaza, carga, decide);
signal actual, proximo:estados;

begin

next_blk: process(start,fin,actual)
begin
case actual is
when espera => if start = '0'
then
proximo<= espera;
else
proximo<= inicia;
end if;
when inicia => proximo <= desplaza;
when desplaza => proximo <= carga;
when carga => proximo <= decide;
when decide => if fin = '0'
 then
proximo <= desplaza;
else
proximo <= espera;
end if;
end case;
end process next_blk;
output_blk: process(actual)
begin
alfa<='0';beta<='0';gama<='0';
case actual is
when espera => null;
when inicia => alfa <='1';
when desplaza => beta <= '1';
when carga => gama <= '1';
when decide => null;
end case;
end process output_blk;

seq_blk: process(clk)
begin
if rising_edge(clk)
then if reset ='1'
then actual <= espera;
else actual <= proximo;
end if;
end if;
end process seq_blk;

end Behavioral;

Multiplexor para el cambio negativo

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux2_1 is
Port ( a,b : in STD_LOGIC_VECTOR (3 downto 0);
sel : in STD_LOGIC;
z : out STD_LOGIC_VECTOR (3 downto 0));
end mux2_1;

architecture Behavioral of mux2_1 is

begin

z<= a when sel='0' else b;

end Behavioral;

Bloque para el cambio de dato a negativo

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity negativo1 is
Port ( dato : in STD_LOGIC_VECTOR (3 downto 0);
z : out STD_LOGIC_VECTOR (3 downto 0));
end negativo1;

architecture Behavioral of negativo1 is

signal s: std_logic_vector(3 downto 0);

begin

s<= (not dato) + ‘1’;

z<=s;

end Behavioral;