library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity microprogramed is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
R : out STD_LOGIC;
Y : out STD_LOGIC;
G : out STD_LOGIC);
end microprogramed;

architecture Behavioral of microprogramed is

type ROM is array (0 to 3) of unsigned (7 downto 0);
constant control_store:ROM:=
(
0=>X"09",--"0000100"
1=>X"52",--"--1010010"
2=>X"DC",--"11011100"
3=>X"06",--"--0000110"
others =>X"00"
);

signal romOut:unsigned (7 downto 0);

alias TEST:std_logic is romOut(7);
alias NSF:unsigned(1 downto 0) is romOut(6 downto 5);
alias NST:unsigned(1 downto 0) is romOut(4 downto 3);
alias OUTPUTS:unsigned(2 downto 0) is romOut(2 downto 0);

signal nsSelect:std_logic;
signal nState:unsigned(1 downto 0);

signal ar:unsigned(1 downto 0);

begin

romOut <= control_store (to_integer(ar));

addReg:process(clk,rst)
begin
if rst='1' then
ar<= "00";
elsif rising_edge(clk) then
ar<=nState;
end if;
end process;

condMux:process(A,B,TEST)
begin
if TEST='0' then
nsSelect <= A;
else
nsSelect <= B;
end if;
end process;

nsMux:process(NSF,NST,nsSelect)
begin
 if nsSelect = '0' then
nState<=NSF;
else
nState<=NST;
end if;
end process;

G<=OUTPUTS(0);
R<=OUTPUTS(1);
Y<=OUTPUTS(2);
end Behavioral;