Digital Integrated Circuit Design: Lecture 1 - History

Digital Integrated Circuit Design
Lecture 1 - History
Adib Abrishamifar
EE Department
IUST
Outline
} History and the road map

} Moore’s Law
} Physical design fundamentals
} Performance issues
IUST: Digital IC Design 2/43 LECTURE 1 : History Adib Abrishamifar 2008

The First Computer
The Babbage
Difference Engine
(1832)
25,000 parts
cost: £17,470

The Invention of Transistor
} John Bardeen, Walter Brattain & Wiliam Shockley

invented “The first transistor” in 1947
First transistor
Bell Labs, 1948

The Invention of Integrated Circuit
} Jack Kilby & Robert Noyce invented “The

Integrated Circuit” in 1958
Bipolar logic
1960’s

The First Electronic (Vacuum Tube) Computer (1946)

Moore’s Law
} In 1965, Gordon Moore (Co-Founder of Intel) predicted that

transistors would continue to shrink, (number of transistors
per chip would grow exponentially) allowing :
I’mBUT,
smiling
} Doubled transistor density every 18-24 months nobecause
exponential
I
Is forever!
} Doubled performance every 18-24 months was right!
} History has proven Moore right

} But, is the end is in sight?
} Physical limitations
} Economic limitations
Gordon Moore
Intel Co-Founder and Chairmain Emeritus
Intel 4004 Micro-Processor
1971
1000 transistors
1 MHz operation
L=10µm

Previous Processors
Pentium® III PowerPC 7400 (G4)

28M transistors / 733MHz-1GHz / 13-26W 6.5M transistors / 450MHz / 8-10W
L=0.25µm shrunk to L=0.18µm L=0.15µm

Previous Processors
Pentium® 4 Pentium® 4 “Northwood”

42M transistors / 1.3-1.8GHz / 49-55W 55M transistors / 2-2.5GHz
L=0.18µm L=0.13µm

Previous Processors
PowerPC® 940 (G5)

58M transistors / 2GHz / 97W
L=0.13µm Area=118mm2
Intel Itanium® 2
410M transistors / 1.3GHz / 130W
L=0.13µm Area=374mm2

Graphics Processors
nVidia GeForce4
57M transistors / 300MHz / L=0.15µm

Current Processors
} Penrym
} 45nm Intel® Core™2 quad-core processors will have 820
million transistors. Thanks to high-k metal transistor
invention, think of 820 million more power efficient light
bulbs going on and off at light-speeds. The dual-core
version has a die size of 107mm2, which is 25 percent
smaller than Intel's current 65nm products

Microprocessor Trends (Intel)
Year Chip L transistors

1971 4004 10µm 2.3K
1974 8080 6µm 6.0K
1976 8088 3µm 29K
1982 80286 1.5µm 134K
1985 80386 1.5µm 275K
1989 80486 0.8µm 1.2M
1993 Pentium® 0.8µm 3.1M
1995 Pentium® Pro 0.6µm 15.5M
1999 Mobile PII 0.25µm 27.4
2000 Pentium® 4 0.18µm 42M
2002 Pentium® 4 (N) 0.13µm 55M

Moore’s law in Microprocessors
1000
100 2X growth in 1.96 years!

Transistors (MT)
10
P6
Pentium® proc
1 486
386
0.1 286
8085 8086
0.01 8080
8008
4004
0.001
1970 1980 1990 2000 2010
Year
Courtesy, Intel
Transistor Counts
1 Billion
K
Transistors
1,000,000
100,000
Pentium® III
10,000 Pentium® II
Pentium® Pro
1,000 Pentium®
i486
100 i386
80286
10 8086
Source: Intel
1
1975 1980 1985 1990 1995 2000 2005 2010
Projected

DRAM Memory Trends (Log Scale)
Source: Textbook, Industry Reports
1000
512
256
100 128
64
16
10
4 Size (Mb)
1 1
0.25
0.1
0.0625
0.01
1975 1980 1985 1990 1995 2000 2005

Evolution in Complexity

Die Size Growth
100
Die size (mm)
P6
486 Pentium ® proc
10 386
286
8080 8086
8085 ~7% growth per year
8008
4004 ~2X growth in 10 years
1
1970 1980 1990 2000 2010
Year
Die
Die size
size grows
grows by
by 14%
14% to
to satisfy
satisfy Moore’s
Moore’s Law
Law
Frequency
10000
Doubles every
1000
2 years
Frequency (Mhz)
100 P6
Pentium ® proc
486
10 8085 386
8086 286
1 8080
8008
4004
0.1
1970 1980 1990 2000 2010
Year
Lead
Lead Microprocessors
Microprocessors frequency
frequency doubles
doubles every
every 22 years
years
Power Dissipation
100
P6
Pentium ® proc
Power (Watts)
10
486
8086 286
386
8085
1 8080
8008
4004
0.1
1971 1974 1978 1985 1992 2000
Year
Lead
Lead Microprocessors
Microprocessors power
power continues
continues to
to increase
increase
Power will be a major problem
100000
18KW
10000 5KW
1.5KW
Power (Watts)
1000 500W
Pentium® proc
100
286 486
10 8086 386
8085
8080
8008
1 4004
0.1
1971 1974 1978 1985 1992 2000 2004 2008
Year
Power
Power delivery
delivery and
and dissipation
dissipation will
will be
be prohibitive
prohibitive
Summary - Technology Trends
} Processor
} Logic capacity increases ~ 30% per year
} Clock frequency increases ~ 20% per year
} Cost per function decreases ~20% per year
} Memory
} DRAM capacity: increases ~ 60% per year
(4x every 3 years)
} Speed: increases ~ 10% per year
} Cost per bit: decreases ~25% per year

What we’re going to do
} Chip design: MOSIS (MOS IC Service)

We Need
} Fabrication Basics: Photolithography

} Processing Steps
} Transistor Structure
} Layout Design

Wafer

Wafer

Mask

The Cost of Fabrication
} Current cost: $2-3 billion

} Typical Fab line occupies about 1 city block,
employs a few hundred people
} Most profitable period is first 18 months-2 years

Cost Factors in ICs
} For large-volume ICs:

} packaging is largest cost
} testing is second-largest cost
} For low-volume ICs, design costs may swamp all
manufacturing costs

Hierarchy of Design Abstractions
English specification
executable system throughput,

program behavior design time
function
sequential function units,
machines Register-transfer clock cycles
Logic gates literals, gate depth,

logic power
cost
transistors circuit nanoseconds
rectangles layout microns

Challenges in Digital Design
µ DSM µ 1/DSM
“Microscopic Problems” “Macroscopic Issues”
• Ultra-high speed design • Time-to-Market
• Interconnect • Millions of Gates
• Noise, Crosstalk • High-Level Abstractions
• Reliability, Manufacturability • Reuse & IP: Portability
• Power dissipation • Predictability
• Clock distribution • etc.
Everything Looks a Little Different

…and There’s a Lot of Them!
?
Why Scaling?
} Technology shrinks by 0.7/generation

} With every generation can integrate 2x more functions per
chip; chip cost does not increase significantly
} Cost of a function decreases by 2x
} But …
} How to design chips with more and more functions?
} Design engineering population does not double every two
years…
} Hence, a need for more efficient design methods
} Exploit different levels of abstraction

Design Abstraction Levels
SYSTEM
MODULE
+
GATE
CIRCUIT
DEVICE
G
S D
n+ n+

Design Metrics
} How to evaluate performance of a digital circuit

(gate, block, …)?
} Cost (Area)
} Reliability
} Scalability
} Speed (delay, operating frequency)
} Power dissipation
} Energy to perform a function

Cost of Integrated Circuits
} NRE (non-recurrent engineering) costs

} design time and effort, mask generation
} one-time cost factor
} Recurrent costs
} silicon processing, packaging, test
} proportional to volume
} proportional to chip area

Die Cost
Single die
Wafer
Going up to 12” (30cm)

Cost per Transistor
cost:
¢-per-
per-transistor
1
0.1 Fabrication capital cost per transistor (Moore’s law)
0.01
0.001
0.0001
0.00001
0.000001
0.0000001
1982 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012

Some Examples (1994)
Chip Metal Line Wafer Def./ Area Dies/w Yield Die
layers width cost cm2 mm2 afer cost
386DX 2 0.90 $900 1.0 43 360 71% $4
486 DX2 3 0.80 $1200 1.0 81 181 54% $12
Power PC 601 4 0.80 $1700 1.3 121 115 28% $53
HP PA 7100 3 0.80 $1300 1.0 196 66 27% $73
DEC Alpha 3 0.70 $1500 1.2 234 53 19% $149
Super Sparc 3 0.70 $1700 1.6 256 48 13% $272
Pentium 3 0.80 $1500 1.5 296 40 9% $417

Technology Trend
International Technology Roadmap

for Semiconductors (ITRS)
Production year 2002 2003 2004 2005 2006 2007
MPU Gate length (nm) 75 65 53 45 40 35
Clock (GHz) 2.3 3.1 4.0 5.2 5.6 6.7
Metal layers 8 8 8 9 9 9
Supply voltage (V) 1.0 1.0 1.0 0.9 0.9 0.7

Performance Issues
} Speed
} Noise
} Clock distribution
} Power distribution
} Low power

Power
1400
Dynamic
1200
power
1000 density
800
mW/mm2
600
400 Leakage
power
200
density
0
0.18 µm 0.13 µm 0.10 µm 0.05 µm
Summary
} Digital integrated circuits have come a long way and still

have quite some potential left for the coming decades
} Some interesting challenges ahead
} Getting a clear perspective on the challenges and potential
solutions is the purpose of this course
} Understanding the design metrics that govern digital
design is crucial
} Cost, reliability, speed, power and energy dissipation

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Digital Integrated Circuit Design

} History and the road map

IUST: Digital IC Design 2/43 LECTURE 1 : History Adib Abrishamifar 2008

IUST: Digital IC Design 3/43 LECTURE 1 : History Adib Abrishamifar 2008

} John Bardeen, Walter Brattain & Wiliam Shockley

IUST: Digital IC Design 4/43 LECTURE 1 : History Adib Abrishamifar 2008

} Jack Kilby & Robert Noyce invented “The

IUST: Digital IC Design 5/43 LECTURE 1 : History Adib Abrishamifar 2008

IUST: Digital IC Design 6/43 LECTURE 1 : History Adib Abrishamifar 2008

} In 1965, Gordon Moore (Co-Founder of Intel) predicted that

} History has proven Moore right

IUST: Digital IC Design 8/43 LECTURE 1 : History Adib Abrishamifar 2008

Pentium® III PowerPC 7400 (G4)

IUST: Digital IC Design 9/43 LECTURE 1 : History Adib Abrishamifar 2008

Pentium® 4 Pentium® 4 “Northwood”

IUST: Digital IC Design 10/43 LECTURE 1 : History Adib Abrishamifar 2008

PowerPC® 940 (G5)

IUST: Digital IC Design 11/43 LECTURE 1 : History Adib Abrishamifar 2008

IUST: Digital IC Design 12/43 LECTURE 1 : History Adib Abrishamifar 2008

IUST: Digital IC Design 13/43 LECTURE 1 : History Adib Abrishamifar 2008

Year Chip L transistors

IUST: Digital IC Design 14/43 LECTURE 1 : History Adib Abrishamifar 2008

100 2X growth in 1.96 years!

IUST: Digital IC Design 16/43 LECTURE 1 : History Adib Abrishamifar 2008

IUST: Digital IC Design 17/43 LECTURE 1 : History Adib Abrishamifar 2008

IUST: Digital IC Design 18/43 LECTURE 1 : History Adib Abrishamifar 2008

IUST: Digital IC Design 23/43 LECTURE 1 : History Adib Abrishamifar 2008

} Chip design: MOSIS (MOS IC Service)

IUST: Digital IC Design 24/43 LECTURE 1 : History Adib Abrishamifar 2008

} Fabrication Basics: Photolithography

IUST: Digital IC Design 25/43 LECTURE 1 : History Adib Abrishamifar 2008

IUST: Digital IC Design 26/43 LECTURE 1 : History Adib Abrishamifar 2008

IUST: Digital IC Design 27/43 LECTURE 1 : History Adib Abrishamifar 2008

IUST: Digital IC Design 28/43 LECTURE 1 : History Adib Abrishamifar 2008

} Current cost: $2-3 billion

IUST: Digital IC Design 29/43 LECTURE 1 : History Adib Abrishamifar 2008

} For large-volume ICs:

IUST: Digital IC Design 30/43 LECTURE 1 : History Adib Abrishamifar 2008

executable system throughput,

Logic gates literals, gate depth,

rectangles layout microns

IUST: Digital IC Design 31/43 LECTURE 1 : History Adib Abrishamifar 2008

Everything Looks a Little Different

} Technology shrinks by 0.7/generation

IUST: Digital IC Design 33/43 LECTURE 1 : History Adib Abrishamifar 2008

IUST: Digital IC Design 34/43 LECTURE 1 : History Adib Abrishamifar 2008

} How to evaluate performance of a digital circuit

IUST: Digital IC Design 35/43 LECTURE 1 : History Adib Abrishamifar 2008

} NRE (non-recurrent engineering) costs

IUST: Digital IC Design 36/43 LECTURE 1 : History Adib Abrishamifar 2008

Going up to 12” (30cm)

IUST: Digital IC Design 37/43 LECTURE 1 : History Adib Abrishamifar 2008

IUST: Digital IC Design 38/43 LECTURE 1 : History Adib Abrishamifar 2008

386DX 2 0.90 $900 1.0 43 360 71% $4

486 DX2 3 0.80 $1200 1.0 81 181 54% $12

Power PC 601 4 0.80 $1700 1.3 121 115 28% $53

HP PA 7100 3 0.80 $1300 1.0 196 66 27% $73

DEC Alpha 3 0.70 $1500 1.2 234 53 19% $149

Super Sparc 3 0.70 $1700 1.6 256 48 13% $272

Pentium 3 0.80 $1500 1.5 296 40 9% $417

IUST: Digital IC Design 39/43 LECTURE 1 : History Adib Abrishamifar 2008

International Technology Roadmap

MPU Gate length (nm) 75 65 53 45 40 35