1

DEPARTMENT OF PHYSICS
GOVERNMENT ARTS COLLEGE
UDHAGAMANDALAM-643202
THE NILGIRIS
(ACCEREDITED WITH *** BY NAAC)

DIGITAL & MICROPROCESSOR RECORD

NAME :
REG. NO :
CLASS :
 2

DEPARTMENT OF PHYSICS
GOVERNMENT ARTS COLLEGE
UDHAGAMANDALAM-643202
THE NILGIRIS
(ACCEREDITED WITH *** BY NAAC)

DIGITAL & MICROPROCESSOR RECORD

Register no.:

CERTIFICATE
This is to Certify that bonafied record of work done by ......................................
during the academic year 2017-2018.

---------------------- ---------------------------
Staff in Charge Head of the Department
Submitted for the practical examination held on ……………… at Government
Arts College,Ooty-643202

----------------------- ----------------------
External Examiner Internal Examiner
 3

EXPT NO.

1. LOGIC GATES

AIM
To verify the logic gates using the truth table

COMPONENTS REQUIRED

S NO. COMPONENTS SPECIFICATIONS QUANTITY

1 IC7404 14 pins 1

2 IC7432 14 pins 1

3 IC7408 14 pins 1

4 IC7400 14 pins 1

5 IC7402 14 pins 1

6 IC7486 14 pins 1

7 DC power supply Western 1

8 Bread board White 1

9 Connecting wires Single core Required quantity

10 Digital multimeter UNI-UT33D 1

11 Voltmeter 0-6v 1
 4

NOT GATE

TRUTH TABLE

Input Voltage:

LOGICAL INPUT LOGICAL OUTPUT MEASURED OUTPUT

A Y= Y(Volts)
0 1
1 0

HIGH VOLTAGE=

LOW VOLTAGE=

LOGIC DIAGRAM
 5

OR GATE

TRUTH TABLE

Input voltage:

LOGICAL INPUT LOGICAL OUTPUT MEASURED OUTPUT

(Volts)

A B Y= Y

0 0 0

0 1 1

1 0 1

1 1 1

HIGH VOLTAGE-

LOW VOLTAGE-

LOGIC SYMBOL
 6

AND GATE

TRUTH TABLE

Input voltage:

LOGICAL INPUT LOGICAL OUTPUT MEASURED OUTPUT

A B Y= Y(Volts)

0 0

0 1

1 0

1 1

High voltage-

Low voltage-

LOGIC SYMBOL
 7

NAND GATE

TRUTH TABLE

Input voltage:

LOGICAL INPUT LOGICAL OUTPUT MEASURED OUTPUT

A B Y= Y(Volts)

0 0

0 1

1 0

1 1

High voltage-

Low voltage-

LOGIC SYMBOL
 8

NOR GATE

TRUTH TABLE

Input voltage:

LOGICAL INPUT LOGICAL OUTPUT MEASURED OUTPUT

A B Y= Y(Volts)

0 0

0 1

1 0

1 1

High voltage=

Low voltage=

LOGIC SYMBOL
 9

EXOR GATE

TRUTH TABLE

Input voltage:

LOGICAL INPUT LOGICAL OUTPUT MEASURED OUTPUT

A B Y= Y(Volts)

0 0

0 1

1 0

1 1

High voltage=

Low voltage=

LOGIC SYMBOL
 10

RESULT

The basic logic gates OR,NOT,AND,NAND,NOR,EXOR are verified using a

multimeter .
 11

EXPT. NO.

2. DEMORGAN’S THEOREM

AIM

To verify the Demorgan’s therem using the truth table

COMPONENTS REQUIRED

S NO. COMPONENTS SPECIFICATIONS QUANTITY

1 IC7404 14 pins 1

2 IC7432 14 pins 1

3 IC7408 14 pins 1

4 DC power supply Western 1

5 Bread board White 1

6 Connecting wires Single core Required quantity

7 Digital multimeter UNS T UT330 1

 12

1st LAW (A.B=A+B)

LHS

TRUTH TABLE

Input voltage:

LOGICAL INPUT LOGICAL OUTPUT MEASURED OUTPUT

A B Y= Y(Volts)

0 0

0 1

1 0

1 1

High voltage=

Low voltage=
 13

RHS

TRUTH TABLE

Input voltage:

LOGICAL INPUT LOGICAL OUTPUT MEASURED OUTPUT

A B Y= Y(Volts)

0 0

0 1

1 0

1 1

High voltage=

Low voltage=
 14

SECOND LAW ( A+B=A.B)

LHS

TRUTH TABLE

Input voltage:

LOGICAL INPUT LOGICAL OUTPUT MEASURED OUTPUT

A B Y= Y(Volts)

0 0

0 1

1 0

1 1

High voltage=

Low voltage=
 15

RHS

TRUTH TABLE

Input voltage:

LOGICAL INPUT LOGICAL OUTPUT MEASURED OUTPUT

A B Y= Y(Volts)

0 0

0 1

1 0

1 1

High voltage=

Low voltage=
 16

RESULT

The Demorgan’s theorems are proved using logic gates.

 17

EXPT NO.:

3. BOOLEAN EXPRESSION

AIM

To verify the given Boolean expression using truth table.

COMPONENTS REQUIRED

S.NO. COMPONENTS SPECIFICATION QUANTITY

1 IC7408 14 pins 1

2 IC7432 14 pins 1

3 DC Power supply Western 1

4 Bread board White 1

5 Connecting wires Single core Required quantity

6 Digital multimeter UNS-T-UT330 1

 18

LOGICAL SYMBOL

TRUTH TABLE

Input voltage:

LOGICAL INPUT LOGICAL OUTPUT MEASURED

OUTPUT

A B C A+B A+C (A+B)(A+C) Y(Volts)

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1
 19

RHS: A+BC

Input voltage:

LOGICAL INPUT LOGICAL OUTPUT MEASURED

OUTPUT

A B C Y=A+BC Y(VOLTS)

0 0 0

0 0 1

0 1 0

1 0 0

1 0 1

1 1 0

1 1 1

High voltage=

Low voltage=
 20

RESULT

The boolean expression is proved using the truth table.

 21

EXPT NO. 4. NAND GATE AS UNIVERSAL BUILDING BLOCK

AND,OR,NOT

AIM

To show that the NAND gate as an universal building block by constructing the
gate using the IC7400 alone and verify the truth table.

COMPONENTS REQUIRED

S.NO. COMPONENTS SPECIFICATIONS QUANTITY

1 IC7400 14 pins 1

2 DC power supply Western 1

3 Bread board General type-white 1

4 Connecting wires Single core Required quantity

5 Multimeter UNS T UT330 1

 22

NAND GATE AS NOT GATE

LOGIC CIRCUIT

TRUTH TABLE

Input voltage:

LOGICAL INPUT LOGICAL OUTPUT MULTIMETER

READINGS
A Y=A Y(Volts)

0 1

1 0
 23

NAND GATE AS AND GATE

LOGIC CIRCUIT

TRUTH TABLE

Input voltage:

LOGICAL INPUT LOGICAL MULTIMETER

OUTPUT READINGS

A B Y=A.B Y(Volts)

0 0

0 1

1 0

1 1

High voltage=

Low voltage=
 24

NAND GATE AS OR GATE

LOGIC CIRCUIT

TRUTH TABLE

Input voltage:

LOGICAL INPUT LOGICAL MULTIMETER

OUTPUT READINGS

A B Y=A.B Y(VOLTS)

0 0

0 1

1 0

1 1

High voltage=

Low voltage=
 25

RESULT

AND,OR,NOT truth tables are proved using NAND gates. By this NAND gate
becomes universal gate.
 26

EXP NO.

5. HALF ADDER

AIM

To construct the half adder circuits and to verify the result using the truth table.

COMPONENTS REQUIRED

S COMPONENTS SPCIFICATIONS QUANTITY

NO.
1 IC7486 14 Pins 1

2 IC7408 14 Pins 1

3 DC Power supply Western(0-9v) 1

4 Bread board General type 1

5 Connecting wires Single core Required quantity

6 Multimeter Digital 1
 27

CIRCUIT DIAGRAM OF HALF ADDER

TRUTH TABLE

Input voltage:
LOGICAL INPUTS LOGICAL OUTPUTS MULTIMETER READING

(Volts)

A B SUM CARRY SUM CARRY

Y= Y=

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

High voltage=

Low voltage=
 28

RESULT

The construction of half adder circuits is verified using truth table.

 29

EXP NO. 6. FULL ADDER

AIM

To construct a full adder circuit and verify using truth table.

COMPONENTS REQUIRED

S NO. COMPONENST SPECIFICATIONS QUANTITY

1 IC7486 14 pins 1

2 IC7408 14 pins 1

3 IC7432 14 pins 1

4 DC power supply Western 1

5 Bread board White 1

6 Connecting wires Single core Required quantity

7 Multimeter UNS –T-UT330 1

 30

CIRCUIT DIAGRAM OF FULL ADDER

TRUTH TABLE

Input voltage:
LOGICAL INPUT LOGICAL OUTPUT MEASURED OUTPUT
(Volts)

A B C SUM CARRY SUM CARRY

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1
 31

RESULT

The construction of full adder circuit is verified using a truth table.

 32

EXPT NO.

7. HALF SUBTRACTOR

AIM:

To construct the half subtractor circuit and to verify the result using truth table.

COMPONENTS REQUIRED:

S.NO. COMPONENTS SPECIFICATION QUANTITY

1 IC7486 14 pins 1

2 IC7408 14 pins 1

3 IC7432 14 pins 1

4 Connecting wire Single core Required quantity

5 DC power supply Western 1

(0-9)v
6 Bread board White 1

7 Digital Multimeter Digital 1

CIRCUIT DIAGRAM OF HALF SUBTRACTOR

 33

TRUTH TABLE

Input voltage:
LOGICAL INPUTS LOGICAL OUTPUTS MULTIMETER READINGS
(Volts)
A B DIFFERENCE BORROW DIFFERENCE BORROW
Y=AB+AB Y=A.B Y Y
0 0

0 1

1 0

1 1

High voltage:

Low voltage:
 34

RESULT

The construction of half and full subtractor circuit is verified using truth table.
 35

EXPT NO.

8.FULL SUBTRACTOR

AIM:

To construct the full subtractor circuit and to verify the result using truth table.

COMPONENTS REQUIRED:

S.NO. COMPONENTS SPECIFICATION QUANTITY

1 IC7486 14 pins 1

2 IC7408 14 pins 1

3 IC7404 14 pins 1

4 IC7432 14 pins 1

5 Connecting wire Single core Required quantity

6 DC power supply Western 1

(0-9)v
7 Bread board White 1

8 Digital Multimeter Digital 1

 36

CIRCUIT DIAGRAM OF FULL SUBTRACTOR

TRUTH TABLE

Input voltage:

LOGICAL INPUTS LOGICAL OUTPUTS MULTIMETER

READINGS(Volts)
A B C DIFFERENCE BORROW

Y=AB+ABC+ Y=AB+AC+ DIFFEREN- BORROW

ABC+ABC BC CE
0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

HIGH VOLTAGE:

LOW VOLTAGE:
 37

RESULT

The construction of full subtractor circuit is verified using truth table.

 38

EXPT NO.

8. RS FLIP FLOP USING IC7400 AND IC7402

AIM:

To construct and verify the truth table of RS flip flop.

COMPONENTS REQUIRED

S NO. COMPONENTS SPECIFICATION QUANTITY

1 IC7400 14 pins 1

2 IC7402 14 pins 1

3 Resistor 470 2

4 LED 2

5 Multimeter Digital 1

6 Connecting wires Single core Required quantity

7 Battery Western 1
 39

CIRCUIT DIAGRAM

TRUTH TABLE

R S Q STATE

0 0

0 1

1 0

1 1

MEASURED VOLTAGE

Input voltage:
INPUT VOLTAGE OUTPUT VOLTAGE STATE
(Volts)
R S Q Q
 40

CIRCUIT DIAGRAM

TRUTH TABLE

R S Q STATE

0 0

0 1

1 0

1 1

MEASURED VOLTAGE

Input voltage:

INPUT VOLTAGE OUTPUT VOLTAGE STATE

(Volts)
R S Q Q
41
 42

RESULT

The RS flip flop is constructed using NOR(IC7402),NAND(IC7400),the output

is verified corresponding to their truth table.

EXPT NO.

8. 8085 ALP FOR 8 BIT ADDITION

AND SUBSTRACTION

AIM:

To add and subtract the two numbers using microprocessor 8085.

ADDITION

OBSERVATION:

Data: 4150=

4151=

Result:4152=

ALGORITHUM

 Load accumulator by 4150

 Move accumulator to register address B,4150
 ADD accumulator with B
 Store the result in 4152
 Read the result at 4152
 43

MEMORY OP CODES MNEMONICS

 44

8 BIT SUBSTRACTION

AIM

To subtract the given number using microprocessor 8085.

OBSERVATION

DATA: 4150=

4151=

RESULT: 4152=

ALGORITHUM

 Initialize memory points to 4150.

 Move the accumulator to register B 4151.
 Subtract accumulator with B.
 Store the result in 4151.
 45

MEMORY ADDRESS QP CODES MNEMONICS

46
 47

RESULT:

8085 ALP for 8 bit is verified.

8085 ALP for 8 bit is verified

EXPT NO. 9. 8 BIT MULTIPLICATION

AIM:

To multiply two numbers residing in memory and store the result in memory.

OBSERVATION:

Data: 4150=

4151=

4152=

4153=

Result: 4154=

4155=

PROGRAM:

LDA 4152 : Load multiplier .

 48

MOV B, A : Get the multiplication to B.

LXI D OOOO : Load register pair immediate.

LHLD 4150 : Load H and L direct.

XCHG : Load multiplication in D and E.

LOOP : DAD D

DCR B

INC LOOP if not zero loop again.

SHLD 4154 LOOP

Else store result

HLT

Mm MEMORY ADDRESS OP CODES MNEMONIC

49
 50

RESULT:

8 bit multiplication is verified.

 51

EXPT NO. 8 BIT DIVISION

AIM:

To divide the 8 bit numbers and to store the result in memory again .

OBSERVATION:

Data: 4150=

4151=

Result: 4152=

4153=

ALGORITHM:

LDA 4150 : Load divider

MOV B,A : To B
LDA 4151 : Load dividend to A
MVIC, 00 : Initialize quotient =0
CMP B
LOOP
LOOP : SUM B; dividend=divisor
INR C : Quotient=quotient+1
CMP B : is dividend<divisor
NC LOOP 1 : if notreapeat again
LOOP : STA 4152;yes then store remainder
MOV A, C
STA 4153; Store quotient
HLT
 52

MEMORY ADDRESS OP CODES MNEMONICS

 53

RESULT:

8 Bit division has been verified

 54

EXPT NO. BIGGEST NUMBER IN AN ARRAY

AIM:

To find the biggest number in an array of 8 bit unsigned numbers. Given the length
of the block.

OBSERVATION:

Data: 4150 =

4151=

4152=

4153=

4154=

4155=

Result: 4156=

PROGRAM:

LXI H, 4150: Point to data start

MOV B,M : Get count to B.

XRA A : Maximum=minimum possible value(zero)

LOOP INXH: Is next number>maximum

CMP M:

INC LOOP I

MOV A, M: yes replace maximum

LOOP I : DCRB: check the length of array

INR LOOP: if b=0 then repeat.

INXH:

MOVE M, A: save maximum number

HLT
 55

MEMORY ADDRESS OP CODE MNEMOMICS

 56

RESULT:

The biggest number in an array of 8 bit numbers is found using microprocessor.