Lecture 17 Finite state machines

General finite state machine (FSM)
FSM: A system that visits a finite
design number of logically distinct states

Moore/Mealy machines

Counters are simple FSMs
 Outputs and states are identical
 Visit states in a fixed sequence without
inputs

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More than counters FSM design

FSMs are typically more complex than
Counter design
FSM design procedure
procedure 1. State diagram
counters 1. State diagram 2. State-transition table
 Outputs can depend on current state and 2. State-transition table 3. State minimization
on inputs 3. Next-state logic 4. State encoding
minimization 5. Next-state logic
 State sequencing depends on current 4. Implement the design minimization
state and on inputs 6. Implement the design

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Example: Vending machine 1. State diagram

Reset (from all states)

15 cents for a cup of coffee

Doesn’t take pennies or quarters S0
N D

Doesn’t provide any change Draw self-loops for
N’ D’ for S0 to S3
Reset S1 S2 Also draw self-loops for
1 for S4 to S8
N D N D

S3 S4 S5 S6
N [open] [open] [open]
Vending Open
Coin Machine Release N D
Sensor FSM Mechanism
D
S7 S8
[open] [open]

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Clock
2. State transition table 3. State minimization
present inputs next output
state D N state open
Reset present inputs next output
S0 0 0 S0 0 N’D’ state D N state open
0 1 S1 0 0¢ 0 0 0¢ 0
1 0 S2 0 0 1 5¢ 0
1 1 X X 0¢ 1 0 10¢ 0
S1 0 0 S1 0 1 1 – –
0 1 S3 0 N’D’ N
1 0 S4 0
5¢ 0 0 5¢ 0
1 1 X X 0 1 10¢ 0
D 1 0 15¢ 0
S2 0 0 S2 0 5¢
0 1 S5 0 1 1 – –
1 0 S6 0 N 10¢ 0 0 10¢
1 1 X X 0 1 15¢ 0
S3 0 0 S3 0 D 10¢ 1 0 15¢ 0
0 1 S7 0 1 1 – –
1 0 S8 0 15¢ – – 15¢ 1
1 1 X X N+D
S4 X X S4 1
S5 X X S5 1 15¢ symbolic state table
S6 X X S6 1 [open] Reset
S7 X X S7 1
S8 X X S8 1
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4. State encoding 5. Next-state logic minimization

Q1 Q1 Q1
D1 D0
D0 Open
present state inputs next state output 0 0 1 1 0 1 1 0
Q1 Q0 D N D1 D0 open 0 0 1 0
0 0 0 0 0 0 0 0 1 1 1 N 1 0 1 1 N 0 0 1 0 N
0 1 0 1 0 X X X X
1 0 1 0 0 D D X X X X D X X 1 X
1 1 – – – 1 1 1 1 0 1 1 1
0 1 0 0 0 1 0 0 0 1 0
0 1 1 0 0 Q0 Q0 Q0
1 0 1 1 0
1 1 – – –
1 0 0 0 1 0 0
D1 = Q1 + D + Q0 N
0 1 1 1 0
1 0 1 1 0
1 1 – – – D0 = Q0’ N + Q0 N’ + Q1 N + Q1 D
1 1 – – 1 1 1
OPEN = Q1 Q0

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6. Implement the design Generalized FSM model

Combinational logic computes next state

and outputs
 Next state is a function of current state and
inputs
 Outputs are functions of

Current state (Moore machine)

Current state and inputs (Mealy machine)
output
Outputs
logic
Inputs
Next-state Next State
logic

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Current State
 Moore vs. Mealy machines State diagrams
Moore machine
inputs Outputs are a function
combinational
logic for of current state
Moore machine
next state logic for
reg outputs
outputs Outputs change  Each state is labeled by a state-
synchronously with
state changes
name/output pair.
state feedback

inputs
logic for
outputs outputs Mealy machine
Mealy machine
Outputs depend on state
combinational
reg
and on inputs  Each transition arc is labeled by a input-
logic for
next state
Input changes can cause condition/output pair.
immediate output changes
state feedback (asynchronous)
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Example: 10  01 Example: "01" or "10" detector

Circuits recognize AB=10 followed by AB=01
Moore: Output is a function of state only
 What kinds of machines are they?  Specify output in the state bubble
current next current
out 0 reset input state state output
A DQ DQ 1 – – A 0
1
Q Q B/0 D/1 0 0 A B 0
B DQ DQ 0 0 1 A C 0
Q Q 0 0 0 B B 0
reset
clock out A/0 1 0 0 1 B D 0
A 0 0 C E 0
Moore D Q 1
1 0 1 C C 0
Q
E/1 0 0 D E 1
B C/0
D Q 0 0 1 D C 1
Q 0 0 E B 1
clock 1
Mealy 15 0 1 E D 116

Example: "01" or "10" detector Moore vs. Mealy

Mealy: Output is a function of state and inputs
Moore machines

 Specify outputs on transition arcs + Safer to use because outputs change at clock
0/0 edge
current next current
reset input state state output – May take additional logic to decode state into
B
0/0 1 – – A 0 outputs
0 0 A B 0
reset/0
0/1 1/1 0 1 A C 0
Mealy machines
A
0 0 B B 0 + Typically have fewer states
0 1 B C 1
1/0
0 0 C B 1 + React faster to inputs — don't wait for clock
C 0 1 C C 0 – Asynchronous outputs can be dangerous
1/0
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Synchronous Mealy machines Synchronous Mealy machines

We often design synchronous Mealy
Registered state and registered outputs

machines  No glitches on outputs
 No race conditions between communicating
 Design a Mealy machine
machines
 Then register the outputs
logic for reg
inputs outputs outputs

combinational
logic for reg
next state

state feedback
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Example: "== 01?"

Recognize AB = 01
 Mealy or Moore?
A
out
D Q
B
clock
Q

Synchronous Mealy
(Moore) A
D Q out

B
D Q
clock
Q
Moore
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