VLSIGURU DFT TRAINING SCAN INSERTION LAB OBSERVATIONS

SCAN INSERTION LAB OBSERVATIONS

Test Case 7: -

Problem Definition: - Design has no ATPG model for a Flip flop used in the netlist,

later create the model and insert scan with 2 scan chains. Inputs: -

  Synthesis Netlist
  Library Model
 Dofile commands
Outputs: -

  Scan inserted Netlist

  ATPG Dofile
  ATPG Testproc
 Scan Def
What is issue?
Ans. Design has no ATPG model for a flip flop used in netlist.
How resolved?
Ans. Modified ATPG library file and create filp flops used in netlist.
Observations: -
1) Write block diagram with all DFT inputs?

Clk

Top Design:
Input Scan Channel EnReg_Buswidth_14_15 Output Scan channel

Scan_En

2) How many clock

domains? Clk

3) How many resets?

There is no Reset pin.

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VLSIGURU DFT TRAINING SCAN INSERTION LAB OBSERVATIONS

4) Number of scan
chains
2 scan chains
Chain 1 :7
Chain 2 :7

5) Clock mixing or not clock mixing?

Not clock mixing

6) How many Lockup-latches are added during scan insertion?

No lockup latches are added during scan insertion.

7) Is it top-down or bottom up approach?

Top-down approach

8) How many terminal lockup latches are

added? zero

9) Number of scan flops and non-scan flops in the design?

14 scannable flops and 0 non scan

10) Chain length? 7 flop per chain

11) Number of DRC violations?

No DRC violation occur.

12) Log file: - please note your observations from the log file
Top module is EnReg_BusWidth_14_15
Number of shift registers =0
Number of new Pins inserted= 5 (scan_in1, scan_in2, scan_en, scan_out1, scan_out2)

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