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M48T08 M48T08Y, M48T18: 5V, 64 Kbit (8 KB x8) TIMEKEEPER Sram
M48T08 M48T08Y, M48T18: 5V, 64 Kbit (8 KB x8) TIMEKEEPER Sram
M48T08 M48T08Y, M48T18: 5V, 64 Kbit (8 KB x8) TIMEKEEPER Sram
M48T08Y, M48T18
FEATURES SUMMARY
■ INTEGRATED ULTRA LOW POWER SRAM, Figure 1. 28-pin PCDIP, CAPHAT™ Package
REAL TIME CLOCK, POWER-FAIL
CONTROL CIRCUIT, AND BATTERY
■ BYTEWIDE™ RAM-LIKE CLOCK ACCESS
■ BCD CODED YEAR, MONTH, DAY, DATE,
HOURS, MINUTES, and SECONDS
■ TYPICAL CLOCK ACCURACY OF ±1
MINUTE A MONTH, AT 25°C 28
■ AUTOMATIC POWER-FAIL CHIP 1
DESELECT AND WRITE PROTECTION
■ WRITE PROTECT VOLTAGES PCDIP28 (PC)
(VPFD = Power-fail Deselect Voltage): Battery/Crystal
CAPHAT
– M48T08: VCC = 4.75 to 5.5V
4.5V ≤ VPFD ≤ 4.75V
– M48T18/T08Y: VCC = 4.5 to 5.5V
4.2V ≤ VPFD ≤ 4.5V Figure 2. 28-pin SOIC Package
■ SOFTWARE CONTROLLED CLOCK
CALIBRATION FOR HIGH ACCURACY SNAPHAT (SH)
APPLICATIONS Battery/Crystal
■ SELF-CONTAINED BATTERY AND
CRYSTAL IN THE CAPHAT™ DIP
PACKAGE
■ PACKAGING INCLUDES A 28-LEAD SOIC
AND SNAPHAT® TOP (to be ordered
separately)
■ SOIC PACKAGE PROVIDES DIRECT
CONNECTION FOR A SNAPHAT TOP 28
WHICH CONTAINS THE BATTERY AND 1
CRYSTAL
■ PIN AND FUNCTION COMPATIBLE WITH SOH28 (MH)
DS1643 and JEDEC STANDARD 8K x8
SRAMs
■ RoHS COMPLIANCE
Lead-free components are compliant with the
RoHS Directive.
M48T08, M48T08Y, M48T18
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. 28-pin PCDIP, CAPHAT™ Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. 28-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. Logic Diagram . . . . . . . . . . . . . . . . . . . . . ....... ...... ....... ...... ...... .....4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . ....... ...... ....... ...... ...... .....4
Figure 4. DIP Connections . . . . . . . . . . . . . . . . . . . ....... ...... ....... ...... ...... .....5
Figure 5. SOIC Connections . . . . . . . . . . . . . . . . . . ....... ...... ....... ...... ...... .....5
Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . ....... ...... ....... ...... ...... .....5
OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 7. READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 8. WRITE Enable Controlled, WRITE AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 9. Chip Enable Controlled, WRITE AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power-fail Interrupt Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
CLOCK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Reading the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Setting the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Stopping and Starting the Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 11.Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 12.Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 6. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 7. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . ...... . . . . 18
Figure 13.AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...... . . . . 18
Table 8. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...... . . . . 18
Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...... . . . . 19
Figure 14.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...... . . . . 20
M48T08, M48T08Y, M48T18
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 16. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 17. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 18. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
M48T08, M48T08Y, M48T18
SUMMARY DESCRIPTION
The M48T08/18/08Y TIMEKEEPER® RAM is an The 28-pin, 330mil SOIC provides sockets with
8K x 8 non-volatile static RAM and real time clock gold plated contacts at both ends for direct con-
which is pin and functional compatible with the nection to a separate SNAPHAT® housing con-
DS1643. The monolithic chip is available in two taining the battery and crystal. The unique design
special packages to provide a highly integrated allows the SNAPHAT battery package to be
battery backed-up memory and real time clock so- mounted on top of the SOIC package after the
lution. completion of the surface mount process. Inser-
The M48T08/18/08Y is a non-volatile pin and func- tion of the SNAPHAT housing after reflow pre-
tion equivalent to any JEDEC standard 8K x 8 vents potential battery and crystal damage due to
SRAM. It also easily fits into many ROM, EPROM, the high temperatures required for device surface-
and EEPROM sockets, providing the non-volatility mounting. The SNAPHAT housing is keyed to pre-
of PROMs without any requirement for special vent reverse insertion.
WRITE timing or limitations on the number of The SOIC and battery/crystal packages are
WRITEs that can be performed. shipped separately in plastic anti-static tubes or in
The 28-pin, 600mil DIP CAPHAT™ houses the Tape & Reel form. For the 28 lead SOIC, the bat-
M48T08/18/08Y silicon with a quartz crystal and a tery/crystal package (e.g., SNAPHAT) part num-
long- life lithium button cell in a single package. ber is “M4T28-BR12SH” or “M4T32-BR12SH”
(see Table 17., page 25).
E2 Chip Enable 2
W
M48T08
M48T08Y G Output Enable
E1 INT
M48T18
W WRITE Enable
E2
VCC Supply Voltage
G
VSS Ground
VSS
AI01020
M48T08, M48T08Y, M48T18
32,768 Hz
CRYSTAL A0-A12
POWER
DQ0-DQ7
8184 x 8
SRAM ARRAY
LITHIUM
CELL E1
VOLTAGE SENSE E2
VPFD
AND
SWITCHING W
CIRCUITRY
G
OPERATION MODES
As Figure 6., page 5 shows, the static memory ar- cells. The M48T08/18/08Y includes a clock control
ray and the quartz-controlled clock oscillator of the circuit which updates the clock bytes with current
M48T08/18/08Y are integrated on one silicon chip. information once per second. The information can
The two circuits are interconnected at the upper be accessed by the user in the same manner as
eight memory locations to provide user accessible any other location in the static memory array.
BYTEWIDE™ clock information in the bytes with The M48T08/18/08Y also has its own Power-fail
addresses 1FF8h-1FFFh. Detect circuit. The control circuitry constantly mon-
The clock locations contain the year, month, date, itors the single 5V supply for an out of tolerance
day, hour, minute, and second in 24 hour BCD for- condition. When VCC is out of tolerance, the circuit
mat. Corrections for 28, 29 (leap year - valid until write protects the SRAM, providing a high degree
2100), 30, and 31 day months are made automat- of data security in the midst of unpredictable sys-
ically. Byte 1FF8h is the clock control register. This tem operation brought on by low VCC. As VCC falls
byte controls user access to the clock information below the Battery Back-up Switchover Voltage
and also stores the clock calibration setting. (VSO), the control circuitry connects the battery
The eight clock bytes are not the actual clock which maintains data and clock operation until val-
counters themselves; they are memory locations id power returns.
consisting of BiPORT™ READ/WRITE memory
READ Mode
The M48T08/18/08Y is in the READ Mode when- available after the latter of the Chip Enable Access
ever W (WRITE Enable) is high, E1 (Chip Enable times (tE1LQV or tE2HQV) or Output Enable Access
1) is low, and E2 (Chip Enable 2) is high. The de- time (tGLQV).
vice architecture allows ripple-through access of The state of the eight three-state Data I/O signals
data from eight of 65,536 locations in the static is controlled by E1, E2 and G. If the outputs are ac-
storage array. Thus, the unique address specified tivated before tAVQV, the data lines will be driven to
by the 13 address inputs defines which one of the an indeterminate state until tAVQV. If the address
8,192 bytes of data is to be accessed. Valid data inputs are changed while E1, E2 and G remain ac-
will be available at the Data I/O pins within address tive, output data will remain valid for Output Data
access time (tAVQV) after the last address input Hold time (tAXQX) but will go indeterminate until the
signal is stable, providing that the E1, E2, and G next address access.
access times are also satisfied. If the E1, E2 and
G access times are not met, valid data will be
tAVAV
A0-A12 VALID
tAVQV tAXQX
tE1LQV tE1HQZ
E1
tE1LQX
tE2HQV tE2LQZ
E2
tE2HQX
tGLQV tGHQZ
tGLQX
DQ0-DQ7 VALID
AI00962
WRITE Mode
The M48T08/18/08Y is in the WRITE Mode when- Enable prior to the initiation of another READ or
ever W, E1, and E2 are active. The start of a WRITE Cycle. Data-in must be valid tDVWH prior to
WRITE is referenced from the latter occurring fall- the end of WRITE and remain valid for tWHDX af-
ing edge of W or E1, or the rising edge of E2. A terward. G should be kept high during WRITE Cy-
WRITE is terminated by the earlier rising edge of cles to avoid bus contention; however, if the output
W or E1, or the falling edge of E2. The addresses bus has been activated by a low on E1 and G and
must be held valid throughout the cycle. E1 or W a high on E2, a low on W will disable the outputs
must return high or E2 low for a minimum of tE1HAX tWLQZ after W falls.
or tE2LAX from Chip Enable or tWHAX from WRITE
tAVAV
A0-A12 VALID
tAVWH
tAVE1L tWHAX
E1
tAVE2H
E2
tWLWH
tAVWL
W
tWLQZ tWHQX
tWHDX
tDVWH
AI00963
M48T08, M48T08Y, M48T18
A0-A12 VALID
tAVE1H
E1
tAVE2L
E2
tAVWL
W
tE1HDX
tE2LDX
tDVE1H
tDVE2L AI00964B
M48T08, M48T08Y, M48T18
CLOCK OPERATIONS
Reading the Clock Setting the Clock
®
Updates to the TIMEKEEPER registers should The eighth bit of the control register is the WRITE
be halted before clock data is read to prevent Bit. Setting the WRITE Bit to a '1,' like the READ
reading data in transition. The BiPORT™ TIME- Bit, halts updates to the TIMEKEEPER registers.
KEEPER cells in the RAM array are only data reg- The user can then load them with the correct day,
isters and not the actual clock counters, so date, and time data in 24 hour BCD format (on Ta-
updating the registers can be halted without dis- ble 5.). Resetting the WRITE Bit to a '0' then trans-
turbing the clock itself. fers the values of all time registers (1FF9h-1FFFh)
Updating is halted when a '1' is written to the to the actual TIMEKEEPER counters and allows
READ Bit, the seventh bit in the control register. normal operation to resume. The FT Bit and the
As long as a '1' remains in that position, updating bits marked as '0' in Table 5. must be written to '0'
is halted. After a halt is issued, the registers reflect to allow for normal TIMEKEEPER and RAM oper-
the count; that is, the day, date, and the time that ation.
were current at the moment the halt command was See the Application Note AN923, “TIMEKEEPER ®
issued. Rolling Into the 21 st Century” for information on
All of the TIMEKEEPER registers are updated si- Century Rollover.
multaneously. A halt will not interrupt an update in
progress. Updating is within a second after the bit
is reset to a '0.'
ppm
20
-20
-40
T0 = 25 °C
-80
-100
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 °C
AI02124
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
M48T08, M48T08Y, M48T18
VCC Noise And Negative Going Transients Figure 12. Supply Voltage Protection
ICC transients, including those produced by output
switching, can produce voltage fluctuations, re-
sulting in spikes on the VCC bus. These transients
can be reduced if capacitors are used to store en-
ergy which stabilizes the VCC bus. The energy
stored in the bypass capacitors will be released as VCC
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic by- VCC
pass capacitor value of 0.1µF (as shown in Figure
12.) is recommended in order to provide the need-
ed filtering. 0.1µF DEVICE
MAXIMUM RATING
Stressing the device above the rating listed in the not implied. Exposure to Absolute Maximum Rat-
“Absolute Maximum Ratings” table may cause ing conditions for extended periods may affect de-
permanent damage to the device. These are vice reliability. Refer also to the
stress ratings only and operation of the device at STMicroelectronics SURE Program and other rel-
these or any other conditions above those indicat- evant quality documents.
ed in the Operating sections of this specification is
PD Power Dissipation 1 W
Note: 1. For DIP package: Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer
than 30 seconds).
2. For SO package, standard (SnPb) lead finish: Reflow at peak temperature of 225°C (total thermal budget not to exceed 180°C for
between 90 to 150 seconds).
3. For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (total thermal budget not to exceed 245°C
for greater than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
M48T08, M48T08Y, M48T18
DC AND AC PARAMETERS
This section summarizes the operating and mea- ment Conditions listed in the relevant tables. De-
surement conditions, as well as the DC and AC signers should check that the operating conditions
characteristics of the device. The parameters in in their projects match the measurement condi-
the following DC and AC Characteristic tables are tions when using the quoted parameters.
derived from tests performed under the Measure-
5V
1.8kΩ
DEVICE
UNDER OUT
TEST
1kΩ CL = 100pF
Table 8. Capacitance
Symbol Parameter(1,2) Min Max Unit
Table 9. DC Characteristics
M48T08/M48T18/T08Y
Symbol Parameter Test Condition(1) Unit
Min Max
ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±1 µA
E1 = VCC – 0.2V,
ICC2(3) Supply Current (Standby) CMOS
E2 = VSS + 0.2V
3 mA
VPFD (min)
VSO
tF tDR tR
tPFX tPFH
INT
trec
HIGH-Z
OUTPUTS VALID VALID
(PER CONTROL INPUT) (PER CONTROL INPUT)
AI00566
Note: Inputs may or may not be recognized at this time. Caution should be taken to keep E1 high or E2 low as VCC rises past VPFD (min).
Some systems may perform inadvertent WRITE cycles after VCC rises above VPFD (min) but before normal system operations begin.
Even though a power on reset is being applied to the processor, a reset condition may not occur until after the system clock is running.
Figure 15. PCDIP28 – 28-pin Plastic DIP, battery CAPHAT, Package Outline
A2 A
A1 L C
B1 B e1
eA
e3
1 PCDIP
Table 12. PCDIP28 – 28-pin Plastic DIP, battery CAPHAT, Package Mechanical Data
mm inches
Symb
Typ Min Max Typ Min Max
A 8.89 9.65 0.350 0.380
A1 0.38 0.76 0.015 0.030
A2 8.38 8.89 0.330 0.350
B 0.38 0.53 0.015 0.021
B1 1.14 1.78 0.045 0.070
C 0.20 0.31 0.008 0.012
D 39.37 39.88 1.550 1.570
E 17.83 18.34 0.702 0.722
e1 2.29 2.79 0.090 0.110
e3 29.72 36.32 1.170 1.430
eA 15.24 16.00 0.600 0.630
L 3.05 3.81 0.120 0.150
N 28 28
M48T08, M48T08Y, M48T18
Figure 16. SOH28 – 28-lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Outline
A2 A
C
B e eB
CP
D
N
E H
A1 α L
1
SOH-A
Table 13. SOH28 – 28-lead Plastic SO, 4-socket battery SNAPHAT, Package Mech. Data
mm inches
Symb
Typ Min Max Typ Min Max
A 3.05 0.120
A1 0.05 0.36 0.002 0.014
A2 2.34 2.69 0.092 0.106
B 0.36 0.51 0.014 0.020
C 0.15 0.32 0.006 0.012
D 17.71 18.49 0.697 0.728
E 8.23 8.89 0.324 0.350
e 1.27 – – 0.050 – –
eB 3.20 3.61 0.126 0.142
H 11.51 12.70 0.453 0.500
L 0.41 1.27 0.016 0.050
α 0° 8° 0° 8°
N 28 28
CP 0.10 0.004
M48T08, M48T08Y, M48T18
Figure 17. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline
A1 A2
A A3
eA B L
eB
D
SHTK-A
Table 14. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mech. Data
mm inches
Symb
Typ Min Max Typ Min Max
A 9.78 0.385
A1 6.73 7.24 0.265 0.285
A2 6.48 6.99 0.255 0.275
A3 0.38 0.015
B 0.46 0.56 0.018 0.022
D 21.21 21.84 0.835 0.860
E 14.22 14.99 0.560 0.590
eA 15.55 15.95 0.612 0.628
eB 3.20 3.61 0.126 0.142
L 2.03 2.29 0.080 0.090
M48T08, M48T08Y, M48T18
Figure 18. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline
A1 A2
A A3
eA B L
eB
D
SHTK-A
Table 15. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data
mm inches
Symb
Typ Min Max Typ Min Max
A 10.54 0.415
A1 8.00 8.51 0.315 .0335
A2 7.24 8.00 0.285 0.315
A3 0.38 0.015
B 0.46 0.56 0.018 0.022
D 21.21 21.84 0.835 0.860
E 17.27 18.03 0.680 .0710
eA 15.55 15.95 0.612 0.628
eB 3.20 3.61 0.126 0.142
L 2.03 2.29 0.080 0.090
M48T08, M48T08Y, M48T18
PART NUMBERING
Device Type
M48T
Speed
–100 = 100ns
–150 = 150ns
–10 = 100ns (M48T08Y)
Package
PC(1) = PCDIP28
MH(2) = SOH28
Temperature Range
1 = 0 to 70°C
Shipping Method
For SOH28:
blank = Tubes (Not for New Design - Use E)
E = ECOPACK Package, Tubes
F = ECOPACK Package, Tape & Reel
TR = Tape & Reel (Not for New Design - Use F)
For PCDIP28:
blank = ECOPACK Package, Tubes
Note: 1. The M48T08/18 part is offered with the PCDIP28 (e.g., CAPHAT™) package only.
2. The SOIC package (SOH28) requires the SNAPHAT ® battery/crystal package which is ordered separately under the part number
“M4TXX-BR12SH” in plastic tube or “M4TXX-BR12SHTR” in Tape & Reel form (see Table 17.). The M48T08Y part is offered in the
SOH28 (SNAPHAT) package only.
Caution: Do not place the SNAPHAT battery package “M4TXX-BR12SH” in conductive foam as it will drain the lithium button-cell bat-
tery.
For other options, or for more information on any aspect of this device, please contact the ST Sales Office
nearest you.
REVISION HISTORY
Reformatted; SNAPHAT battery table added (Table 17); added temp./voltage info. to
16-Jul-01 3.0
tables (Tables 8, 9, 3, 4, 10, 11)
01-Aug-01 3.1 Reference to App. Note corrected in “Calibrating the Clock” section
21-Dec-01 3.2 Changes to text in document to reflect addition of M48T08Y option
06-Mar-02 3.3 Fix Ordering Information table and add to footnote (Table 16)
20-May-02 3.4 Modify reflow time and temperature footnotes (Table 6)
29-Aug-02 3.5 tDR specification temperature updated (Table 11)
28-Mar-03 4.0 v2.2 template applied; updated test conditions (Table 10)
10-Dec-03 5.0 Reformatted
30-Mar-04 6.0 Reformatted; Lead-free (Pb-free) information package update (Table 6, 16)
13-Dec-05 7.0 Updated template, Lead-free information, removed footnote (Table 9, 16)