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Scan Insertion Lab Observations
Scan Insertion Lab Observations
Synthesis Netlist
Library Model
Dofile commands
Outputs: -
What is issue?
Ans. Design has 3 S2 violations
How resolved?
Ans.Set test logic –set on –reset on –clock on =>dofile command adds required mux
and inverter gates to clear DRC violations
Observations: -
1) Write block diagram with all DFT inputs?
FastClk
Reset
Vlsiguru Confidential 1
VLSIGURU DFT TRAINING SCAN INSERTION LAB OBSERVATIONS
Vlsiguru Confidential 2
VLSIGURU DFT TRAINING SCAN INSERTION LAB OBSERVATIONS
14) Log file: - please note your observations from the log file
Ans.Top module is DmaWr
Number of shift registers =2
Number of MUX inserted =3
Number of new Pins inserted= 4 (1 scan inputs, 1 scan outputs, scan_en, test_en )
Vlsiguru Confidential 3