/////////////////////////////////////////////////////////////

// Created by: Synopsys DC Expert(TM) in wire load mode

// Version : M-2016.12-SP5-1
// Date : Fri Dec 14 14:45:02 2018
/////////////////////////////////////////////////////////////

module DmaWr_edt_decompressor ( edt_clock, edt_update, edt_channels_in,

edt_scan_in );
input edt_clock, edt_update, edt_channels_in;
output edt_scan_in;
wire N0, N1, N2, N3, N4, N5, lfsm_vec_lockup_0, n4, n5, n6, n7;
wire [7:0] lfsm_vec;
wire [4:3] lfsm_vec_lockup;

INVX1 U6 ( .A(edt_update), .Y(n4) );

DFFNSRX1 \lfsm_vec_lockup_reg[4] ( .D(lfsm_vec[4]), .CKN(edt_clock), .SN(
1'b1), .RN(1'b1), .Q(lfsm_vec_lockup[4]) );
DFFNSRX1 \lfsm_vec_lockup_reg[3] ( .D(lfsm_vec[3]), .CKN(edt_clock), .SN(
1'b1), .RN(1'b1), .Q(lfsm_vec_lockup[3]) );
DFFNSRX1 \lfsm_vec_lockup_reg[0] ( .D(lfsm_vec[0]), .CKN(edt_clock), .SN(
1'b1), .RN(1'b1), .Q(lfsm_vec_lockup_0) );
DFFTRX1 \lfsm_vec_reg[7] ( .D(N5), .RN(n4), .CK(edt_clock), .Q(lfsm_vec[7])
);
DFFTRX1 \lfsm_vec_reg[6] ( .D(N4), .RN(n4), .CK(edt_clock), .Q(lfsm_vec[6])
);
DFFTRX1 \lfsm_vec_reg[5] ( .D(N3), .RN(n4), .CK(edt_clock), .Q(lfsm_vec[5])
);
DFFTRX1 \lfsm_vec_reg[1] ( .D(N0), .RN(n4), .CK(edt_clock), .Q(lfsm_vec[1])
);
DFFTRX1 \lfsm_vec_reg[2] ( .D(lfsm_vec[3]), .RN(n4), .CK(edt_clock), .Q(
lfsm_vec[2]) );
DFFTRX1 \lfsm_vec_reg[0] ( .D(lfsm_vec[1]), .RN(n4), .CK(edt_clock), .Q(
lfsm_vec[0]) );
DFFTRX1 \lfsm_vec_reg[4] ( .D(N2), .RN(n4), .CK(edt_clock), .Q(lfsm_vec[4])
);
DFFTRX1 \lfsm_vec_reg[3] ( .D(N1), .RN(n4), .CK(edt_clock), .Q(lfsm_vec[3])
);
XOR2X1 U7 ( .A(edt_channels_in), .B(lfsm_vec[2]), .Y(N0) );
XOR2X1 U8 ( .A(edt_channels_in), .B(n7), .Y(N1) );
XOR2X1 U9 ( .A(lfsm_vec[4]), .B(lfsm_vec[3]), .Y(n7) );
XOR2X1 U10 ( .A(lfsm_vec[0]), .B(edt_channels_in), .Y(N5) );
XOR2X1 U11 ( .A(lfsm_vec[2]), .B(n6), .Y(N2) );
XOR2X1 U12 ( .A(lfsm_vec[5]), .B(lfsm_vec[3]), .Y(n6) );
XOR2X1 U13 ( .A(lfsm_vec[6]), .B(N0), .Y(N3) );
XOR2X1 U14 ( .A(lfsm_vec[7]), .B(lfsm_vec[1]), .Y(N4) );
XOR2X1 U15 ( .A(lfsm_vec_lockup[3]), .B(n5), .Y(edt_scan_in) );
XOR2X1 U16 ( .A(lfsm_vec_lockup_0), .B(lfsm_vec_lockup[4]), .Y(n5) );
endmodule

module DmaWr_edt_compactor ( edt_scan_out, masks_for_compactor_0,

edt_channels_out );
input edt_scan_out, masks_for_compactor_0;
output edt_channels_out;

AND2X2 U1 ( .A(masks_for_compactor_0), .B(edt_scan_out), .Y(edt_channels_out) );

endmodule
module DmaWr_edt_xor_decoder ( encoded_masks, decoded_masks_0 );
input encoded_masks;
output decoded_masks_0;

CLKBUFX3 U1 ( .A(encoded_masks), .Y(decoded_masks_0) );

endmodule

module DmaWr_edt_onehot_decoder_1_to_1 ( encoded_masks, decoded_masks );

input encoded_masks;
output decoded_masks;

CLKBUFX3 U1 ( .A(encoded_masks), .Y(decoded_masks) );

endmodule

module DmaWr_edt_controller ( edt_clock, edt_update, edt_channels_in,

edt_channels_out_from_controller, masks_for_compactor_0 );
input edt_clock, edt_update, edt_channels_in;
output edt_channels_out_from_controller, masks_for_compactor_0;
wire \masks_shift_reg_0[1] , xor_decoded_masks_0, onehot_decoded_masks_0,
n1, n2;
wire [1:0] masks_hold_reg_0;

DmaWr_edt_xor_decoder xor_decoder ( .encoded_masks(masks_hold_reg_0[0]),

.decoded_masks_0(xor_decoded_masks_0) );
DmaWr_edt_onehot_decoder_1_to_1 decoder1 ( .encoded_masks(
masks_hold_reg_0[0]), .decoded_masks(onehot_decoded_masks_0) );
INVX1 U3 ( .A(edt_update), .Y(n1) );
EDFFX1 \masks_hold_reg_0_reg[1] ( .D(\masks_shift_reg_0[1] ), .E(edt_update),
.CK(edt_clock), .Q(masks_hold_reg_0[1]), .QN(n2) );
EDFFX1 \masks_hold_reg_0_reg[0] ( .D(edt_channels_out_from_controller), .E(
edt_update), .CK(edt_clock), .Q(masks_hold_reg_0[0]) );
DFFTRX1 \masks_shift_reg_0_reg[0] ( .D(\masks_shift_reg_0[1] ), .RN(n1),
.CK(edt_clock), .Q(edt_channels_out_from_controller) );
DFFTRX1 \masks_shift_reg_0_reg[1] ( .D(edt_channels_in), .RN(n1), .CK(
edt_clock), .Q(\masks_shift_reg_0[1] ) );
AO22X1 U4 ( .A0(xor_decoded_masks_0), .A1(n2), .B0(onehot_decoded_masks_0),
.B1(masks_hold_reg_0[1]), .Y(masks_for_compactor_0) );
endmodule

module DmaWr_edt_bypass_logic ( edt_bypass, edt_channels_in, edt_channels_out,

edt_scan_in, edt_scan_out, edt_bypass_in, edt_bypass_out );
input edt_bypass, edt_channels_in, edt_scan_out, edt_bypass_in,
edt_bypass_out;
output edt_channels_out, edt_scan_in;
wire n1;

AO22X1 U1 ( .A0(edt_channels_in), .A1(edt_bypass), .B0(edt_bypass_in), .B1(

n1), .Y(edt_scan_in) );
AO22X1 U2 ( .A0(edt_scan_out), .A1(edt_bypass), .B0(edt_bypass_out), .B1(n1),
.Y(edt_channels_out) );
CLKINVX1 U3 ( .A(edt_bypass), .Y(n1) );
endmodule
module DmaWr_edt ( edt_clock, edt_update, edt_bypass, edt_channels_in,
edt_channels_out, edt_scan_in, edt_scan_out );
input edt_clock, edt_update, edt_bypass, edt_channels_in, edt_scan_out;
output edt_channels_out, edt_scan_in;
wire edt_channels_out_from_controller, edt_bypass_in,
masks_for_compactor_0, edt_bypass_out;

DmaWr_edt_decompressor DmaWr_edt_decompressor_i ( .edt_clock(edt_clock),

.edt_update(edt_update), .edt_channels_in(
edt_channels_out_from_controller), .edt_scan_in(edt_bypass_in) );
DmaWr_edt_compactor DmaWr_edt_compactor_i ( .edt_scan_out(edt_scan_out),
.masks_for_compactor_0(masks_for_compactor_0), .edt_channels_out(
edt_bypass_out) );
DmaWr_edt_controller DmaWr_edt_controller_i ( .edt_clock(edt_clock),
.edt_update(edt_update), .edt_channels_in(edt_channels_in),
.edt_channels_out_from_controller(edt_channels_out_from_controller),
.masks_for_compactor_0(masks_for_compactor_0) );
DmaWr_edt_bypass_logic DmaWr_edt_bypass_logic_i ( .edt_bypass(edt_bypass),
.edt_channels_in(edt_channels_in), .edt_channels_out(edt_channels_out),
.edt_scan_in(edt_scan_in), .edt_scan_out(edt_scan_out),
.edt_bypass_in(edt_bypass_in), .edt_bypass_out(edt_bypass_out) );
endmodule

/* Generated by Tessent Shell 2016.3 at Wed Dec 12 17:41:52 2018 */

module DmaWr(DmaOut, PmaOut, PMSel, PMWr, DMSel, DMWr, IACKbarOut, IncCr, PmdIn,
DmdIn, CountWr_r, ProcClk, FastClk, Reset, ISbar, IWrbar, IADIn,
IDMACrOut,
PMAccGnt, DMAccGnt, St34, St56, IDMACrInLat, IDMACrWrLat, IALIn,
IDMACrWrCore,
CountRd_r, test_en, scan_en, edt_clock, edt_update, edt_bypass,
edt_channels_in1,
edt_channels_out1);
input [15:0] IADIn, IDMACrOut, IDMACrInLat;
input [1:0] CountRd_r;
input ProcClk, FastClk, Reset, ISbar, IWrbar, PMAccGnt, DMAccGnt, St34,
St56, IDMACrWrLat, IALIn, IDMACrWrCore, test_en, scan_en, edt_clock,
edt_update, edt_bypass, edt_channels_in1;
output [23:0] PmdIn;
output [15:0] DmdIn;
output [13:0] DmaOut, PmaOut;
output [1:0] CountWr_r;
output PMSel, PMWr, DMSel, DMWr, IACKbarOut, IncCr, edt_channels_out1;

wire [2:0] CurrentState, NextState;

wire scan_in1, scan_out1, net9, net8, net7, net6, net5, net4, net3, net2,
net1, n290, StartWr, N43, N44, MemWrSync1, N49, LoadWrbuffer, PMSel_r,
DMSel_r, PMWr_r, DMWr_r, n77, n90, n91, n92, n93, n103, n109, n125,
n126, n127, n128, n129, n130, n131, n132, n133, n134, n135, n136, n137,
n138, n139, n140, n141, n142, n143, n144, n145, n146, n147, n148, n151,
n154, n155, net207063, net207064, net207065, net207057, net207045,
net207044, net207036, net207033, net207032, net207031, net207029,
net207028, net207026, net207024, net207023, net206976, net206971,
net206966, net206963, net206961, net206954, net218273, net218368,
net218626, net237473, net251629, net253343, net253550, net253576,
net253574, net253622, net253621, net253897, net253896, net253899,
net253910, net254025, net252313, net206959, net206952, net206951,
net254692, net254691, net206973, net206972, net206968, net298903,
 net301373, net245854, net207022, net207038, net206969, net207021,
net253894, net253694, net206955, net206953, net310218, net254013,
net207046, net260022, net248389, net206956, net252024, net246509,
net207055, net207053, net207052, net207035, net207034, net207025,
net206975, n166, n167, n168, n169, n170, n171, n172, n173, n174, n175,
n176, n177, n178, n179, n180, n181, n182, n183, n184, n185, n186, n187,
n188, n190, n193, n195, n197, n199, n201, n203, n205, n207, n209, n211,
n213, n215, n217, n219, n221, n223, n225, n228, n231, n234, n237, n240,
n243, n246, n249, n252, n255, n258, n261, n264, n267, n268, n269, n270,
n271, n272, n273, n274, n275, n276, n277, n278, n279, n280, n281, n282,
n283, n284, n285, n286, n287, n288, n289;

assign scan_out1 = CountWr_r[1];

MX2XL uu3(.Y(net3), .A(1'b0), .B(FastClk), .S0(test_en));
MX2XL uu2(.Y(net2), .A(1'b0), .B(FastClk), .S0(test_en));
MX2XL uu1(.Y(net1), .A(1'b0), .B(FastClk), .S0(test_en));
SDFFSX4 DMSel_r_reg(.Q(DMSel_r), .QN(net6), .D(n290), .SI(net253576),
.SE(scan_en),
.CK(FastClk), .SN(Reset));
SDFFRX4 CurrentState_reg_2_(.Q(CurrentState[2]), .QN(net253576),
.D(NextState[2]),
.SI(net251629), .SE(scan_en), .CK(FastClk), .RN(Reset));
SDFFRX4 CurrentState_reg_1_(.Q(CurrentState[1]), .QN(net251629),
.D(NextState[1]),
.SI(net7), .SE(scan_en), .CK(FastClk), .RN(Reset));
NAND3BX4 U66(.Y(n90), .AN(n103), .B(DMAccGnt), .C(net253550));
NAND2BX4 U72(.Y(n91), .AN(PMAccGnt), .B(n109));
OAI211X4 U89(.Y(n77), .A0(DMAccGnt), .A1(n103), .B0(net253574), .C0(n167));
SDFFRX4 CountWr_r_reg_0_(.Q(CountWr_r[0]), .QN(net218273), .D(n154),
.SI(PmdIn[7]),
.SE(scan_en), .CK(FastClk), .RN(Reset));
SDFFSX1 PMSel_r_reg(.Q(PMSel_r), .QN(net7), .D(net298903), .SI(net8),
.SE(scan_en),
.CK(FastClk), .SN(Reset));
DFFRX1 StartWrClkd_reg(.Q(net4), .QN(n166), .D(StartWr), .CK(FastClk),
.RN(Reset));
SDFFRX1 StartWr_reg(.Q(StartWr), .QN(), .D(N44), .SI(net5), .SE(scan_en),
.CK(FastClk), .RN(Reset));
SDFFQX1 IDmaWrbufOut_reg_7_(.Q(PmdIn[7]), .D(n132), .SI(PmdIn[6]), .SE(scan_en),
.CK(FastClk));
SDFFQX1 IDmaWrbufOut_reg_6_(.Q(PmdIn[6]), .D(n131), .SI(PmdIn[5]), .SE(scan_en),
.CK(FastClk));
SDFFQX1 IDmaWrbufOut_reg_5_(.Q(PmdIn[5]), .D(n130), .SI(PmdIn[4]), .SE(scan_en),
.CK(FastClk));
SDFFQX1 IDmaWrbufOut_reg_4_(.Q(PmdIn[4]), .D(n129), .SI(PmdIn[3]), .SE(scan_en),
.CK(FastClk));
SDFFQX1 IDmaWrbufOut_reg_3_(.Q(PmdIn[3]), .D(n128), .SI(PmdIn[2]), .SE(scan_en),
.CK(FastClk));
SDFFQX1 IDmaWrbufOut_reg_2_(.Q(PmdIn[2]), .D(n127), .SI(PmdIn[1]), .SE(scan_en),
.CK(FastClk));
SDFFQX1 IDmaWrbufOut_reg_1_(.Q(PmdIn[1]), .D(n126), .SI(PmdIn[0]), .SE(scan_en),
.CK(FastClk));
SDFFQX1 IDmaWrbufOut_reg_0_(.Q(PmdIn[0]), .D(n125), .SI(DmdIn[15]), .SE(scan_en),

.CK(FastClk));
SDFFQX1 IDmaWrbufOut_reg_23_(.Q(DmdIn[15]), .D(n148), .SI(DmdIn[14]),
.SE(scan_en),
.CK(FastClk));
SDFFQX1 IDmaWrbufOut_reg_22_(.Q(DmdIn[14]), .D(n147), .SI(DmdIn[13]),
.SE(scan_en),
.CK(FastClk));
SDFFQX1 IDmaWrbufOut_reg_21_(.Q(DmdIn[13]), .D(n146), .SI(DmdIn[12]),
.SE(scan_en),
.CK(FastClk));
SDFFQX1 IDmaWrbufOut_reg_20_(.Q(DmdIn[12]), .D(n145), .SI(DmdIn[11]),
.SE(scan_en),
.CK(FastClk));
SDFFQX1 IDmaWrbufOut_reg_19_(.Q(DmdIn[11]), .D(n144), .SI(DmdIn[10]),
.SE(scan_en),
.CK(FastClk));
SDFFQX1 IDmaWrbufOut_reg_18_(.Q(DmdIn[10]), .D(n143), .SI(DmdIn[9]),
.SE(scan_en),
.CK(FastClk));
SDFFQX1 IDmaWrbufOut_reg_17_(.Q(DmdIn[9]), .D(n142), .SI(DmdIn[8]), .SE(scan_en),

.CK(FastClk));
SDFFQX1 IDmaWrbufOut_reg_16_(.Q(DmdIn[8]), .D(n141), .SI(DmdIn[7]), .SE(scan_en),

.CK(FastClk));
SDFFQX1 IDmaWrbufOut_reg_15_(.Q(DmdIn[7]), .D(n140), .SI(DmdIn[6]), .SE(scan_en),

.CK(FastClk));
SDFFQX1 IDmaWrbufOut_reg_14_(.Q(DmdIn[6]), .D(n139), .SI(DmdIn[5]), .SE(scan_en),

.CK(FastClk));
SDFFQX1 IDmaWrbufOut_reg_13_(.Q(DmdIn[5]), .D(n138), .SI(DmdIn[4]), .SE(scan_en),

.CK(FastClk));
SDFFQX1 IDmaWrbufOut_reg_12_(.Q(DmdIn[4]), .D(n137), .SI(DmdIn[3]), .SE(scan_en),

.CK(FastClk));
SDFFQX1 IDmaWrbufOut_reg_11_(.Q(DmdIn[3]), .D(n136), .SI(DmdIn[2]), .SE(scan_en),

.CK(FastClk));
SDFFQX1 IDmaWrbufOut_reg_10_(.Q(DmdIn[2]), .D(n135), .SI(DmdIn[1]), .SE(scan_en),

.CK(FastClk));
SDFFQX1 IDmaWrbufOut_reg_9_(.Q(DmdIn[1]), .D(n134), .SI(DmdIn[0]), .SE(scan_en),
.CK(FastClk));
SDFFQX1 IDmaWrbufOut_reg_8_(.Q(DmdIn[0]), .D(n133), .SI(IncCr), .SE(scan_en),
.CK(FastClk));
SDFFRX1 IncCr_reg(.Q(IncCr), .QN(), .D(N49), .SI(scan_in1), .SE(scan_en),
.CK(net1), .RN(Reset));
DFFRX1 StartSyncWr_reg(.Q(n289), .QN(net5), .D(MemWrSync1), .CK(net2),
.RN(Reset));
SDFFSX1 PMWr_r_reg(.Q(PMWr_r), .QN(net8), .D(PMWr), .SI(net9), .SE(scan_en),
.CK(FastClk), .SN(1'b1));
SDFFSX1 DMWr_r_reg(.Q(DMWr_r), .QN(net9), .D(DMWr), .SI(net253343), .SE(scan_en),

.CK(FastClk), .SN(1'b1));
SDFFRX1 MemWrSync1_reg(.Q(MemWrSync1), .QN(), .D(net310218), .SI(net6),
.SE(scan_en), .CK(net3), .RN(Reset));
SDFFRHQX4 IntIdmaWr_r_reg(.Q(net253343), .D(net310218), .SI(net253896),
.SE(scan_en), .CK(FastClk), .RN(Reset));
SDFFRHQX8 CurrentState_reg_0_(.Q(net253896), .D(NextState[0]), .SI(IACKbarOut),
.SE(scan_en), .CK(FastClk), .RN(Reset));
SDFFRHQX4 CountWr_r_reg_1_(.Q(CountWr_r[1]), .D(n155), .SI(net4), .SE(scan_en),
.CK(FastClk), .RN(Reset));
 SDFFRX4 IACKbarOut_reg(.Q(IACKbarOut), .QN(n171), .D(n151), .SI(CountWr_r[0]),
.SE(scan_en), .CK(FastClk), .RN(Reset));
OAI2BB1X2 U3(.Y(net310218), .A0N(net252024), .A1N(net253343), .B0(net206975));
INVX2 U4(.Y(net253694), .A(n173));
NOR3X4 U5(.Y(net253574), .A(net253576), .B(net253896), .C(net251629));
NAND3X1 U6(.Y(n173), .A(net260022), .B(net206961), .C(net253574));
AND2X2 U7(.Y(n167), .A(net218626), .B(net206961));
AND2X4 U8(.Y(net237473), .A(net206969), .B(net206961));
INVX3 U9(.Y(net253894), .A(net218273));
MXI2X2 U10(.Y(n154), .A(net206963), .B(n190), .S0(net253899));
OAI2BB1X2 U11(.Y(net301373), .A0N(CurrentState[1]), .A1N(net206968), .B0(n185));
NAND2X1 U12(.Y(net206968), .A(net206969), .B(CurrentState[1]));
NAND2X2 U13(.Y(n185), .A(n184), .B(n186));
AND2X2 U14(.Y(n186), .A(n168), .B(net206968));
INVX6 U15(.Y(net207022), .A(net207038));
NOR2X1 U16(.Y(net206966), .A(net206956), .B(net206954));
OR2X1 U17(.Y(net254691), .A(net254692), .B(net206971));
NAND2X1 U18(.Y(net207036), .A(PMSel_r), .B(DMSel_r));
NAND2X1 U19(.Y(net252024), .A(n178), .B(net246509));
INVX3 U20(.Y(net207046), .A(net253574));
INVX1 U21(.Y(net206971), .A(CurrentState[1]));
INVX1 U22(.Y(net253897), .A(net253896));
NAND2X1 U23(.Y(n190), .A(n180), .B(n181));
NOR2X1 U24(.Y(net206963), .A(net206954), .B(net301373));
AND3X1 U25(.Y(n168), .A(net206955), .B(net206972), .C(net206973));
OR3X1 U26(.Y(net252313), .A(net206961), .B(net206954), .C(net206956));
OR2X1 U27(.Y(n170), .A(net207044), .B(net207045));
INVX3 U28(.Y(n184), .A(IDMACrWrCore));
OAI2BB1X2 U29(.Y(net206951), .A0N(n172), .A1N(n185), .B0(net206959));
AND2X1 U30(.Y(n172), .A(net254691), .B(net252313));
NAND2X2 U31(.Y(n155), .A(net206951), .B(net206952));
NAND3X1 U32(.Y(n178), .A(n174), .B(net253550), .C(IDMACrOut[14]));
INVX1 U33(.Y(n174), .A(DMAccGnt));
NAND2X1 U34(.Y(net207023), .A(n176), .B(PMWr_r));
NAND2X1 U35(.Y(net207057), .A(n176), .B(DMWr_r));
NAND2X1 U36(.Y(n177), .A(n176), .B(PMSel_r));
BUFX2 U37(.Y(n176), .A(n77));
NAND2X2 U38(.Y(n175), .A(n77), .B(DMSel_r));
NAND3X2 U39(.Y(DMSel), .A(n175), .B(net206954), .C(net218368));
NAND2X4 U40(.Y(net245854), .A(n77), .B(PMSel_r));
AND3X1 U41(.Y(net246509), .A(n91), .B(net206956), .C(net207052));
MXI2X1 U42(.Y(net207052), .A(net206954), .B(net207053), .S0(net253574));
MXI2X1 U43(.Y(net207053), .A(net260022), .B(net207055), .S0(net207035));
INVX1 U44(.Y(net207035), .A(net206961));
MXI2X1 U45(.Y(net207032), .A(net207033), .B(net207034), .S0(net207035));
NOR2X1 U46(.Y(net207055), .A(n169), .B(net207034));
INVX1 U47(.Y(net207034), .A(St34));
NOR3X1 U48(.Y(net207044), .A(net207046), .B(net206961), .C(net207034));
INVX2 U49(.Y(n103), .A(IDMACrOut[14]));
NAND4X1 U50(.Y(net206975), .A(StartWr), .B(net253896), .C(net206971),
.D(net207025));
NAND2X1 U51(.Y(n151), .A(net206975), .B(net206976));
INVX1 U52(.Y(net207025), .A(CurrentState[2]));
OAI21X1 U53(.Y(NextState[0]), .A0(net207031), .A1(net207025),
.B0(CurrentState[1]));
OAI22X1 U54(.Y(NextState[2]), .A0(net207024), .A1(net207025), .B0(net206971),
.B1(net207026));
NAND2X1 U55(.Y(net207029), .A(net207028), .B(net207025));
NAND3X6 U56(.Y(net207038), .A(n91), .B(net206954), .C(n90));
 NOR2X1 U57(.Y(net206953), .A(net206955), .B(net206956));
NAND2X2 U58(.Y(net254013), .A(net260022), .B(net206961));
NAND2X1 U59(.Y(net206956), .A(net253896), .B(CurrentState[1]));
NAND2X8 U60(.Y(net206954), .A(net253896), .B(n179));
NAND2X6 U61(.Y(n179), .A(CurrentState[2]), .B(CurrentState[1]));
NAND2X4 U62(.Y(net260022), .A(net206969), .B(net206955));
NAND2X6 U63(.Y(net206961), .A(net253894), .B(net248389));
INVX3 U64(.Y(net248389), .A(CountWr_r[1]));
NAND2X2 U65(.Y(net206959), .A(net301373), .B(net248389));
MXI2X4 U67(.Y(net206969), .A(IDMACrOut[14]), .B(IDMACrInLat[14]),
.S0(IDMACrWrLat));
NOR2X4 U68(.Y(net253550), .A(net254013), .B(net207046));
NAND2X1 U69(.Y(net218368), .A(n103), .B(net253550));
NAND2X2 U70(.Y(net207021), .A(net253694), .B(n103));
BUFX2 U71(.Y(net254025), .A(net253694));
NAND2X2 U73(.Y(net218626), .A(net206969), .B(net206955));
OAI21X1 U74(.Y(net206952), .A0(net206953), .A1(net206954), .B0(CountWr_r[1]));
NAND2X4 U75(.Y(net206955), .A(net218273), .B(CountWr_r[1]));
INVX3 U76(.Y(n109), .A(net207021));
INVX1 U77(.Y(net207045), .A(n90));
NAND2X8 U78(.Y(PMSel), .A(net207022), .B(net245854));
BUFX2 U79(.Y(net253910), .A(net207022));
NAND2X1 U80(.Y(net298903), .A(net253910), .B(n177));
NAND2X2 U81(.Y(n180), .A(n184), .B(n183));
OR2X1 U82(.Y(n181), .A(n182), .B(n188));
INVX1 U83(.Y(n182), .A(net253621));
AND2X2 U84(.Y(n183), .A(n168), .B(net253621));
INVX1 U85(.Y(net254692), .A(net206968));
NOR2X1 U86(.Y(net206973), .A(CountRd_r[1]), .B(IALIn));
INVX1 U87(.Y(net206972), .A(CountRd_r[0]));
OR2X1 U88(.Y(net253621), .A(net253622), .B(net206968));
INVX1 U90(.Y(net253899), .A(CountWr_r[0]));
NAND2X1 U91(.Y(n187), .A(net254025), .B(n103));
INVX1 U92(.Y(net253622), .A(net206966));
AND2X1 U93(.Y(n188), .A(net206971), .B(net206966));
BUFX2 U94(.Y(net207065), .A(net237473));
BUFX2 U95(.Y(net207063), .A(net237473));
BUFX2 U96(.Y(net207064), .A(net237473));
INVX1 U97(.Y(n288), .A(PMAccGnt));
INVX1 U98(.Y(DmaOut[13]), .A(n264));
INVX1 U99(.Y(DmaOut[0]), .A(n225));
INVX1 U100(.Y(DmaOut[12]), .A(n261));
INVX1 U101(.Y(DmaOut[1]), .A(n228));
INVX1 U102(.Y(DmaOut[2]), .A(n231));
INVX1 U103(.Y(DmaOut[3]), .A(n234));
INVX1 U104(.Y(DmaOut[4]), .A(n237));
INVX1 U107(.Y(DmaOut[5]), .A(n240));
INVX1 U108(.Y(DmaOut[6]), .A(n243));
INVX1 U109(.Y(DmaOut[7]), .A(n246));
INVX1 U110(.Y(DmaOut[8]), .A(n249));
INVX1 U111(.Y(DmaOut[10]), .A(n255));
INVX1 U112(.Y(DmaOut[11]), .A(n258));
INVX1 U113(.Y(DmaOut[9]), .A(n252));
INVX1 U114(.Y(PmdIn[16]), .A(n209));
INVX1 U115(.Y(PmdIn[17]), .A(n211));
INVX1 U116(.Y(PmdIn[18]), .A(n213));
INVX1 U117(.Y(PmdIn[19]), .A(n215));
INVX1 U118(.Y(PmdIn[20]), .A(n217));
INVX1 U119(.Y(PmdIn[21]), .A(n219));
INVX1 U120(.Y(PmdIn[22]), .A(n221));
INVX1 U121(.Y(PmdIn[23]), .A(n223));
INVX1 U122(.Y(PmdIn[8]), .A(n193));
INVX1 U123(.Y(PmdIn[9]), .A(n195));
INVX1 U124(.Y(PmdIn[10]), .A(n197));
INVX1 U125(.Y(PmdIn[11]), .A(n199));
INVX1 U126(.Y(PmdIn[12]), .A(n201));
INVX1 U127(.Y(PmdIn[13]), .A(n203));
INVX1 U128(.Y(PmdIn[14]), .A(n205));
INVX1 U129(.Y(PmdIn[15]), .A(n207));
INVX1 U130(.Y(PmaOut[0]), .A(n225));
INVX1 U131(.Y(PmaOut[1]), .A(n228));
INVX1 U132(.Y(PmaOut[2]), .A(n231));
INVX1 U133(.Y(PmaOut[3]), .A(n234));
INVX1 U134(.Y(PmaOut[4]), .A(n237));
INVX1 U135(.Y(PmaOut[5]), .A(n240));
INVX1 U136(.Y(PmaOut[6]), .A(n243));
INVX1 U137(.Y(PmaOut[7]), .A(n246));
INVX1 U138(.Y(PmaOut[8]), .A(n249));
INVX1 U139(.Y(PmaOut[9]), .A(n252));
INVX1 U140(.Y(PmaOut[10]), .A(n255));
INVX1 U141(.Y(PmaOut[11]), .A(n258));
INVX1 U142(.Y(PmaOut[12]), .A(n261));
INVX1 U143(.Y(PmaOut[13]), .A(n264));
MX2X1 U144(.Y(n141), .A(IADIn[8]), .B(DmdIn[8]), .S0(net207063));
MX2X1 U145(.Y(n142), .A(IADIn[9]), .B(DmdIn[9]), .S0(net207063));
MX2X1 U146(.Y(n143), .A(IADIn[10]), .B(DmdIn[10]), .S0(net207063));
MX2X1 U147(.Y(n144), .A(IADIn[11]), .B(DmdIn[11]), .S0(net207063));
MX2X1 U148(.Y(n145), .A(IADIn[12]), .B(DmdIn[12]), .S0(net207063));
MX2X1 U149(.Y(n146), .A(IADIn[13]), .B(DmdIn[13]), .S0(net207063));
MX2X1 U150(.Y(n147), .A(IADIn[14]), .B(DmdIn[14]), .S0(net207063));
MX2X1 U151(.Y(n148), .A(IADIn[15]), .B(DmdIn[15]), .S0(net207064));
MXI2X1 U152(.Y(n125), .A(n283), .B(n275), .S0(net207065));
INVX1 U153(.Y(n283), .A(PmdIn[0]));
MXI2X1 U154(.Y(n126), .A(n282), .B(n274), .S0(net207064));
INVX1 U155(.Y(n282), .A(PmdIn[1]));
MXI2X1 U156(.Y(n127), .A(n281), .B(n273), .S0(net207065));
INVX1 U157(.Y(n281), .A(PmdIn[2]));
MXI2X1 U158(.Y(n128), .A(n280), .B(n272), .S0(net207064));
INVX1 U159(.Y(n280), .A(PmdIn[3]));
MXI2X1 U160(.Y(n129), .A(n279), .B(n271), .S0(net207065));
INVX1 U161(.Y(n279), .A(PmdIn[4]));
MXI2X1 U162(.Y(n130), .A(n278), .B(n270), .S0(net207064));
INVX1 U163(.Y(n278), .A(PmdIn[5]));
MXI2X1 U164(.Y(n131), .A(n277), .B(n269), .S0(net207065));
INVX1 U165(.Y(n277), .A(PmdIn[6]));
MXI2X1 U166(.Y(n132), .A(n276), .B(n268), .S0(net207064));
INVX1 U167(.Y(n276), .A(PmdIn[7]));
MXI2X1 U168(.Y(n133), .A(n275), .B(n193), .S0(net207065));
MXI2X1 U169(.Y(n134), .A(n274), .B(n195), .S0(net207064));
MXI2X1 U170(.Y(n135), .A(n273), .B(n197), .S0(net207065));
MXI2X1 U171(.Y(n136), .A(n272), .B(n199), .S0(net207064));
MXI2X1 U172(.Y(n137), .A(n271), .B(n201), .S0(net207065));
MXI2X1 U173(.Y(n138), .A(n270), .B(n203), .S0(net207064));
MXI2X1 U174(.Y(n139), .A(n269), .B(n205), .S0(net207065));
MXI2X1 U175(.Y(n140), .A(n268), .B(n207), .S0(net207063));
NAND2X1 U176(.Y(net207033), .A(St56), .B(net207036));
NAND2X1 U177(.Y(net206976), .A(n267), .B(IACKbarOut));
NAND2X1 U178(.Y(net207026), .A(n289), .B(net253897));
INVX1 U179(.Y(net207024), .A(net207028));
INVX1 U180(.Y(n225), .A(IDMACrOut[0]));
NAND2X1 U181(.Y(net207028), .A(net206971), .B(n284));
INVX1 U182(.Y(n228), .A(IDMACrOut[1]));
INVX1 U183(.Y(n231), .A(IDMACrOut[2]));
INVX1 U184(.Y(n234), .A(IDMACrOut[3]));
INVX1 U185(.Y(n237), .A(IDMACrOut[4]));
INVX1 U186(.Y(n240), .A(IDMACrOut[5]));
INVX1 U187(.Y(n243), .A(IDMACrOut[6]));
INVX1 U188(.Y(n246), .A(IDMACrOut[7]));
INVX1 U189(.Y(n249), .A(IDMACrOut[8]));
INVX1 U190(.Y(n255), .A(IDMACrOut[10]));
INVX1 U191(.Y(n258), .A(IDMACrOut[11]));
INVX1 U192(.Y(n261), .A(IDMACrOut[12]));
INVX1 U193(.Y(n264), .A(IDMACrOut[13]));
OAI2BB1X1 U194(.Y(NextState[1]), .A0N(CurrentState[1]), .A1N(net253897),
.B0(net207029));
INVX1 U195(.Y(n252), .A(IDMACrOut[9]));
INVX1 U196(.Y(n209), .A(DmdIn[8]));
INVX1 U197(.Y(n211), .A(DmdIn[9]));
INVX1 U198(.Y(n213), .A(DmdIn[10]));
INVX1 U199(.Y(n215), .A(DmdIn[11]));
INVX1 U200(.Y(n217), .A(DmdIn[12]));
INVX1 U201(.Y(n219), .A(DmdIn[13]));
INVX1 U202(.Y(n221), .A(DmdIn[14]));
INVX1 U203(.Y(n223), .A(DmdIn[15]));
INVX1 U204(.Y(n193), .A(DmdIn[0]));
INVX1 U205(.Y(n195), .A(DmdIn[1]));
INVX1 U206(.Y(n197), .A(DmdIn[2]));
INVX1 U207(.Y(n199), .A(DmdIn[3]));
INVX1 U208(.Y(n201), .A(DmdIn[4]));
INVX1 U209(.Y(n203), .A(DmdIn[5]));
INVX1 U210(.Y(n205), .A(DmdIn[6]));
INVX1 U211(.Y(n207), .A(DmdIn[7]));
INVX1 U212(.Y(n275), .A(IADIn[0]));
INVX1 U213(.Y(n274), .A(IADIn[1]));
INVX1 U214(.Y(n273), .A(IADIn[2]));
INVX1 U215(.Y(n272), .A(IADIn[3]));
INVX1 U216(.Y(n271), .A(IADIn[4]));
INVX1 U217(.Y(n270), .A(IADIn[5]));
INVX1 U218(.Y(n269), .A(IADIn[6]));
INVX1 U219(.Y(n268), .A(IADIn[7]));
AND4X1 U220(.Y(N44), .A(n171), .B(n92), .C(n93), .D(n166));
INVX1 U221(.Y(n93), .A(IWrbar));
AOI21X1 U222(.Y(LoadWrbuffer), .A0(n285), .A1(n286), .B0(n166));
OAI21X1 U223(.Y(n285), .A0(n287), .A1(n170), .B0(StartWr));
NAND2X1 U224(.Y(PMWr), .A(net207023), .B(net253910));
AO21X1 U225(.Y(N43), .A0(IWrbar), .A1(ISbar), .B0(n166));
NAND3X1 U226(.Y(n286), .A(IWrbar), .B(IACKbarOut), .C(ISbar));
INVX1 U227(.Y(n92), .A(ISbar));
NOR2X1 U228(.Y(n287), .A(n187), .B(n288));
NAND3X1 U229(.Y(DMWr), .A(net206954), .B(n187), .C(net207057));
NAND3X1 U230(.Y(n290), .A(net206954), .B(n187), .C(n175));
NOR2X1 U231(.Y(net207031), .A(net253896), .B(net207032));
NAND2X1 U232(.Y(n267), .A(net253896), .B(net206971));
NAND2X1 U233(.Y(n284), .A(StartWr), .B(net253896));
NAND2X1 U234(.Y(N49), .A(net298903), .B(n290));
DmaWr_edt DmaWr_edt_i(.edt_clock(edt_clock), .edt_update(edt_update),
.edt_bypass(edt_bypass), .edt_channels_in(edt_channels_in1),
 .edt_channels_out(edt_channels_out1), .edt_scan_in(scan_in1),
.edt_scan_out(scan_out1));
endmodule